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Ixiasoft
1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
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Ixiasoft
5.1. Features
Features for Advanced Clocking Mode design example includes:
- Support up to 16 lanes for 17.4 Gbps and 4 lanes for 28 Gbps transceiver data rate
- Support for duplex transmission modes
- Traffic checker for data verification and lane de-skew verification
- Support for CRC error injection using Nios® V processor
- Slave test mode for master and slave testing