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1. Quick Start Guide
2. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Standard Clocking Mode Design Example
3. Detailed Description for Stratix® 10 H-tile and L-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
4. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Standard Clocking Mode Design Example
5. Detailed Description for Stratix® 10 E-tile Serial Lite III Streaming Advanced Clocking Mode Design Example
6. Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide Archives
7. Document Revision History for Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide
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Ixiasoft
2.3.1.6. Demo Management
The demo management module controls the user modules interaction with the Serial Lite III Streaming IP core such as enable and disable traffic generator and traffic checker, enable CRC error insertion, and provide user clock reset for Serial Lite III Streaming IP core. The module also implements CSRs to control and monitor the design operation. This includes CSRs to monitor and log errors that occur during the operation.