DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022
Public

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Document Table of Contents

13.1.1.2. Updated Help

After you run a simulation, DSP Builder updates the help pages with specific information about each instance of a block. This updated help overrides the default help link. To find the updated help click on the help link on the block after simulation.

This updated help includes a link back to the help for the general block and the following information about the generated FIR instance:

  • Date and time of generation
  • The version number and revision for the FIR
  • Number of physical input and output data buses
  • Bit width of data output.
  • Number of different phases
  • Implementation folding. The number of times that the design uses each multiplier per sample to reduce the implementation size.
  • Filter utilization. For some sample rates and some interpolation/decimation settings, the filter may stall internally one or more cycles. The filter utilization is the percentage of time that the filter is actively working, assuming that the input arrives at the specified data rate.
  • Tap utilization. When some filters are folded, the design may have extra unused taps. The extra taps increase the filter length with no hardware resource increase.
  • Latency. The depth of pipelining added to the block to meet the target clock frequency on the chosen target device.
  • Parameters table that lists the system clock, clock margin, and all FIR input parameters.
  • Port interface table.
  • Input and output data format. An ASCII rendering of the input and output channelized data ordering.

The updated help includes the following information about the CIC instance:

  • Date and time of generation
  • The version number and revision for the CIC
  • Number of integrators. Depending on the input data rate and interpolation factor the number of integrator stages DSP Builder needs to process the data may be more than 1. In these instances, the integrator sections of the filter duplicate (vectorize) to satisfy the data rate requirement.
  • Calculated output bit width. The width in bits of the (vectorized) data output from the filter.
  • Calculated stage bit widths. Each stage in the filter has precise width in bits requirements—N comb sections followed by N integrator sections.
  • The gain through the CIC filter. CIC filters usually have large gains that you must scale back.
  • Comb section utilization. In the comb section, the data rate is lower, so that you can perform more resource sharing. This message indicates the efficiency of the subtractor usage.
  • Integrator section utilization. In the integrator section, the data rate is higher, so that you can perform less resource sharing. This message indicates the efficiency of the adder usage.
  • The latency that this block introduces.
  • Parameters table that lists the decimation rate, number of stages, differential delay, number of channels, clock frequency, and input sample rate parameters.
  • Port interface table.
  • Input and output data format.