DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022
Public

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7.12.12. Gaussian Random Number Generator

This DSP Builder design example demonstrates a random number generator (CLT component method) that produces random numbers with normal distribution and standard deviation that you specify using the input sigma_input.

You can also specify the seed value for the random sequence using the seed_value input. The reset input resets the sequence to the initial state defined by the seed_value. The output is a 32-bit single-precision floating-point number.