DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.13.15. Crest Factor Reduction

This reference design implements crest factor reduction, based on the peak cancelling algorithm.

For further information refer to the web page.

You can change the simulation length by clicking on the Simulink Length block.

The model file is demo_cfr.mdl.