DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 5/27/2022
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15.3.14. Hybrid FFT (Hybrid_FFT, HybridVFFT, HybridVFFT_btb)

The hybrid FFT blocks implement a hybrid serial or parallel implementation of a supersampled FFT (or IFFT) that processes 2M points per cycle (where M>0).

The hybrid FFT has a parallel section and an optional serial section. You control the length of the serial section by a parameter. Generally, the serial section is more memory-efficient and the parallel section is more DSP-efficient. Therefore, changing the value of this parameter provides a trade-off between DSP memory usage and block usage. The hybrid FFT includes three blocks:

  • Fixed size Hybrid_FFT
  • Variable size HybridVFFT
  • Variable size back-to-back HybridVFFT_btb

HybridVFFT and HybridVFFT_btb have different behaviours when the FFT size changes. Different size FFTs take different numbers of cycles to compute, so that, without additional measures, the smaller FFT overtakes the tail of the larger FFT and the output is corrupted. In this situation, DSP Builder can:

  • Stop-and-flush. Depending on the current size, you can bypass certain stages of the FFT pipeline. You must ensure a sufficient gap between inputs of different size so that no overtaking occurs.
  • Queue-and-wait. All FFTs take the same number of cycles. Smaller FFTs, instead of bypassing parts of the pipeline, just go through delay lines in the stages that don't affect them. You have no constraints on providing gaps in the input.

The HybridVFFT uses stop-and-flush, which achieves the lowest possible latency for small FFTs. HybridVFFT_btb uses queue-and-wait. It can process FFTs continuously, with no breaks required when the FFT size changes, and no busy periods when it cannot accept new inputs.

The demo_variable_hybridfft.mdl example design demonstrates HybridVFFT.

Table 123.  Common Parameters for the Hybrid_FFT, HybridVFFT and HybridVFFT_btb Blocks
Parameter Description
IFFT

Specify if the operation is an FFT or an inverse FFT.

Specify true for an inverse FFT; false for an FFT.

Bit-reversed input

Specify if the input is in natural or bit-reversed order.

Specify true for the IP to receive its input in bit-reversed order and to produce its output in natural order. Specify false for the IP to receive its input in natural order and to produce its output in bit-reversed order.

M Specify the number of parallel inputs/wires where the number of wires is 2 M . For example, a value of 1 means 2 parallel data inputs and a value of 5 means 32 parallel data inputs.
Input type

Input Type is the MATLAB type of the input data. For example, fixdt(1,16,15) or single.

Twiddle/pruning specification Refer to About Pruning and Twiddle for FFT Blocks section.
Optimize twiddle memory usage

Specify whether the block should reduce twiddle memory at the expense of other resources such as logic and DSP blocks.

Specify true to reduce memory.

Use faithful rounding

Specify whether the block should use faithful or correct rounding for floating point operations. Specify true for faithful rounding and false for correct rounding.

This parameter allows you to trade-off accuracy against resource usage. Select correct rounding for maximum accuracy and faithful rounding for reduced resource usage.

DSP Builder ignores this parameter for fixed-point operations.

Table 124.  Additional Parameters for the HybridVFFT Block
Parameter Description
N

Specify the size of the FFT where the FFT size is 2 N .

For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT.

N cannot be smaller than M.

Number of serial stages

Specify the number of serial stages of the hybrid architecture.

The hybrid architecture consists of zero-or-more serial stages combined with one-or-more parallel stages.

This number controls the architecture that implements the FFT and affects its resource usage and latency.

Number of serial stages must be in the range 0 to N-M.

Table 125.  Additional Parameters for the HybridVFFT_btb Block
Parameter Description
maxsize

Specify the maximum size of the FFT, where the maximum size of the FFT is 2 maxsize .

For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT.

minsize

Specify minimum the size of the FFT, where the minimum size of the FFT is 2 minsize .

For example, a value of 0 represents a 1 point FFT and 16 represents a 64K point FFT.

minsize cannot be smaller than M.

Number of serial stages for maximum FFT size

Specify the number of serial stages of the hybrid architecture.

The hybrid architecture consists of zero-or-more serial stages combined with one-or-more parallel stages.

This number controls the architecture that implements the FFT and affects its resource usage and latency.

The serial stages implement the variability of the FFT. Ensure the design has at least (maxsizeminsize) number of serial stages for the maximum FFT size.

Number of serial stages for maximum FFT size must be in the range (maxsize-minsize) to maxsize-M.

Table 126.  Common Port Interfaces for the Hybrid_FFT, HybridVFFT, and HybridVFFT_btb Blocks
Signal Direction Type Description
v Input Boolean.

Data valid signal. Assert this signal when input data is valid.

This signal must not deassert during an FFT. Keep it asserted from the first input to last input of an FFT.

d Input As specified by Input Type.

Data input signal.

A vector of complex input data signals of the user-specified type (Input Type).

qv Output Boolean. Data valid signal. The block asserts this signal for valid output data.
q Output Determined by pruning specification.

Data output signal.

A vector of complex output data signals of the user-specified type (Input Type).

Table 127.  Additional Port Interface for the HybridVFFT Block
Signal Direction Type Description
size Input

Unsigned integer.

Width is determined by maxsize.

The size of the current FFT, where the FFT size is 2 size . For example, a value of 2 represents a 4-point FFT and 16 represents a 64K-point FFT.

The size must be within the user specified range of minsize and maxsize.

Table 128.  Additional Port Interfaces for the HybridVFFT_btb Block
Signal Direction Type Description
size Input

Unsigned integer.

Width is determined by maxsize.

The size of the current FFT, where the FFT size is 2 size . For example, a value of 2 represents a 4-point FFT and 16 represents a 64K-point FFT.

The size must be within the user specified range of minsize and maxsize.

sop Input Boolean

Start of packet signal.

Use this signal to indicate the start of an FFT input frame.

This signal must be high for one cycle at the start of a frame.

qsize Output

Unsigned integer.

Width is determined by maxsize.

The size of the current FFT, where the size of FFT is 2 qsize

For example, a value of 2 represents a 4 point FFT and 16 represents a 64K point FFT.

qsop Output Boolean

Start of packet signal.

The block asserts this Boolean signal on the first (and only the first) valid output of an FFT/IFFT.