Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

45.4. Video Frame Reader IP Registers

Each register is either read-only (RO) or read-write (RW).

Main register set

Table 833.  Video Frame Reader IP Registers

In the software API, the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_VIDEO FRAME READER as appropriate and with an optional REG suffix

Address Register Access Description
Parameterization registers
0x0000 VID_PID RO Read this register for the Video Frame Reader product ID. This register always returns 0x6AF7_024A.
0x0004 VERSION RO Read this register for the IP version information.
0x0008 LITE_MODE RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO Read this register to determine if Debug features is on.
0x0010 MAX_BUFFER_SETS RO Read this register to determine the maximum supported number of buffer sets.
0x0014 MAX_HEIGHT RO Read this register to determine the maximum supported frame height.
0x0018 MAX_WIDTH RO Read this register to determine the maximum supported frame width.
0x001C BITS_PER_SYMBOL RO Read this register for the number of bits per symbol configured.
0x0020 NUMBER_OF_COLOR_PLANES RO Read this register for the number of color planes.
0x0024 PIXELS_IN_PARALLEL RO Read this register for the number of pixels in parallel.
0x0028 PACKING RO Read this register for the pixel packing scheme.

0x002C to 0x00FF

Reserved
Interrupt registers
0x0100 IRQ_CONTROL RW

Set bit 0 to 1 to enable interrupts on completion of field reads

0x0104 IRQ_STATUS RW

Read the status register to see if the interrupt fired. If it did, the IP sets bit 0. To clear the interrupt, write a 1 to bit 0.

0x0107 to 0x013F

Reserved.
Control and Debug Registers
0x0140 STATUS RO

Bit 0: status bit.

1 = Video Frame Reader is outputting a video field, 0 otherwise.

Bit 1: Pending RTC control bit. Goes high when a write occurs to one of the control registers. Goes low at the end of the current frame if the IP makes a write to the COMMIT register.

0x0144 LAST_BUFFER_READ RO Returns the base address of the frame that the IP last produced. This register returns 0xFFFF_FFFF if the IP reads no buffers since reset.
0x0147-0x018F Reserved
0x0190 COMMIT RW Commit register.
0x0194 NUM_BUFFER_SETS RW

Instructs the frame reader how many buffer sets to configure.

0x0198 BUFFER_MODE RW Buffer mode.
0x019C STARTING_BUFFER_SET RW Starting buffer set.
0x01A0 RUN RW

Set the required operating mode:

0 = Frame reader is not running (stopped)

1 = Frame reader is free-running mode.

2 = Frame reader is in frame sync mode. In this mode the reader starts the output on receiving a frame sync and stops when the field is output.

3 = Frame reader is in single-shot mode. In this mode, BUFFER_N_NUM_BUFFERS decides how many buffers are read from. After the IP reads all the buffers from the current set (or all sets if BUFFER_MODE is set to 1), output stops. To perform another single-shot read, write to the COMMIT register.

0x01A4 FSYNC_PULSE_MODE RW Frame sync pulse mode.

Buffer set register banks

In addition to the main register set, the IP has one bank of registers per configured buffer set. Program the buffer set register banks with the relevant details for each set. The IP calculates the base address in hex for each register bank according to the buffer set number, which is an integer from 0 to MAX_BUFFER_SETS:

For example, buffer set 0 registers are at 0x01B0 + 0 = 0x01B0.

For example, buffer set 1 registers are at 0x01B0 + 1x 0x40 = 0x01F0.

For example, buffer set 3 registers are at 0x01B0 + 3x 0x40 = 0x0270.

Table 834.  Buffer set register banks
Address Register Access Description
0x01B0 + N*0x40 BUFFER_N_BASE RW Buffer base address
0x01B4 + N*0x40 BUFFER_N_NUM_BUFFERS RW Number of buffers in this buffer set. Often set to 1 for common double-buffering applications.
0x01B8 + N*0x40 BUFFER_N_INTER_BUFFER_OFFSET RW

Interbuffer address increment.

If BUFFER_N_NUM_BUFFERS is set to 1, this register is unused.

0x01BC + N*0x40 BUFFER_N_INTER_LINE_OFFSET RW Interline address increment.
0x01C0 + N*0x40 BUFFER_N_WIDTH RW For outgoing image information packets if Lite mode is off.
0x01C4 + N*0x40 BUFFER_N_HEIGHT RW For outgoing image information packets if Lite mode is off and to determine how many lines to read from the BASE address.
0X01C8 + N*0x40 BUFFER_N_INTERLACE RW For outgoing image information packets if Lite mode is off and to set TUSER[1] unless BUFFER_0_PACKED_INTERLACE is non-zero.
0x01CC + N*0x40 BUFFER_N_COLORSPACE RW For outgoing image information packets if Lite mode is off.
0x01D0 + N*0x40 BUFFER_N_SUBSAMPLING RW For outgoing image information packets if Lite mode is off.
0x01D4 + N*0x40 BUFFER_N_COSITING RW For outgoing image information packets if Lite mode is off.
0x01D8 + N*0x40 BUFFER_N_BPS RW For outgoing image information packets if Lite mode is off.
0x01DC + N*0x40 BUFFER_N_FIELD_COUNT RW For outgoing image information (low 7 bits) and EOF packets for field count quantities if Lite mode is off.

Register Bit Descriptions

Table 835.  VID_PID
Name Bits Description
Frame reader version ID and product ID 31:0

This register always returns 0x6AF7_024A

  • 15:0 is the product ID and always returns 0x024A
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 836.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 837.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on lite mode.
Unused 31:1 Unused.
Table 838.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 839.  MAX_BUFFER_SETS
Name Bits Description
Max buffer sets 5:0 This register returns the maximum supported number of buffer sets.
Table 840.  MAX_WIDTH
Name Bits Description
Max width 31:0 This register returns the maximum supported frame width.
Table 841.  MAX_HEIGHT
Name Bits Description
Max height 31:0 This register returns the maximum supported frame height.
Table 842.  BITS_PER_SYMBOL
Name Bits Description
Bits per symbol 31:0 This register returns the number of bits per symbol that the Intel streaming video output is configured for.
Table 843.  NUMBER_OF_COLOR_PLANES
Name Bits Description
Number of color planes 31:0 This register returns the number of color planes that the Intel streaming video output is configured for.
Table 844.  PIXELS_IN_PARALLEL
Name Bits Description
Number of pixels in parallel 31:0 This register returns the number of pixels in parallel that the Intel streaming video output is configured for.
Table 845.  PACKING
Name Bits Description
Packing 31:0

This register returns the packing scheme that the IP uses:

  • 0 = Perfect packing
  • 1 = Color packing
  • 2 = Pixel packing
Table 846.   IRQ_CONTROL
Name Bit Description
Field_read_irq 0

Set the field_read_irq bit of the IRQ_CONTROL register to enable interrupts on completing field reads.

Clear to disable interrupts on completion of field reads

Table 847.   IRQ_STATUS
Name Bit Description
Field_read_irq 0

The field_read_irq bit of the IRQ_CONTROL register is set if the interrupt has fired.

Write to the field_read_irq bit of the IRQ_CONTROL register to clear down any interrupts.

Table 848.  STATUS
Name Bit Description
Status 0 Read this register to determine the status of the frame reader. The status bit is set if the reader is currently outputting a frame and returns to 0 in between frames.
Pending run-time control 1 Read this register to determine whether any pending register writes exist that have yet to be committed. This bit goes high when a write occurs to one of the control registers and returns low at the end of the current frame when a write has been made to the COMMIT register. If the frame reader is idle, this bit goes low directly after a write to the COMMIT register.
Table 849.  LAST_BUFFER_READ
Name Bit Description
Last buffer read 31:0 Read this register to determine the base address of the most recent output buffer. After a reset, if no buffers appear, this register returns 0xFFFF_FFFF.
Table 850.  COMMIT
Name Bit Description
Commit 0 Write to this register to commit the current register settings. The IP starts operating according to the new settings when it produces the current frame.
Table 851.  NUM_BUFFER_SETS
Name Bits Description
Number of buffer sets 31:0

Set this register to the number of buffer sets that you want.

The IP reads from buffers within each buffer set in turn.

For a typical memory-mapped graphics double buffer application, you might set up two buffer sets, each containing just one buffer. Software tick-tocks between the buffers under API control using the STARTING_BUFFER_SET register.

Legal values are between 1 and the maximum number of buffer sets you set in the GUI. To save area, the maximum number of buffer sets you set in the GUI restricts the number of buffer sets that the IP can use, as each set requires its own bank of registers. Setting this register to a value greater than MAX_BUFFER_STRUCTURES means the IP configures only one buffer set.

This register is the number of buffer sets that the IP actively uses. Do not confuse it with the maximum number of buffer sets you set in the GUI.

Table 852.  BUFFER_MODE
Name Bit Description
Buffer mode 1

Set this register according to the behavior you want:

0 = Read buffers in STARTING_BUFFER_SET only.

1 = Reads all buffer sets in turn, starting at STARTING_BUFFER_SET.

Table 853.  STARTING_BUFFER_SET
Name Bits Description
Starting buffer set 31:0 Set this register to a value from 0 to NUM_BUFFER_SETS to identify the starting buffer set.

Set this register to indicate the buffer set that you want to read from. For example, to read the first buffer from the buffer set at BUFFER_3_BASE, set this register to 3.

When starting reading from a new set, the first buffer in the set is output first.

Read LAST_BUFFER_READ(0x0144)to determine which buffer from the set was last read and output.

Reading starts from a new buffer set according to this register from STARTING_BUFFER_SET with the COMMIT register.

Table 854.  RUN
Name Bit Description
Run LSB 0

Set this bit to start the IP.

Clear this bit and clear the MSB to halt the IP.

Run MSB 1

If the LSB is set and this bit is clear, the IP operates in continuous (free-running) mode.

If the LSB is set, set this bit to configure the IP in single-shot mode. In this mode, BUFFER_N_NUM_BUFFERS dictates how many buffers are read from the current set, N. After the IP reads all the buffers from the current set (if BUFFER_MODE is set to 1), output stops. To perform another single-shot read, write to the COMMIT register.

If the LSB is clear, clear this bit to stop the IP at the end of the current frame read.

If the LSB is clear, set this bit to configure frame sync mode. In this mode, the reader produces one frame per frame sync.

Table 855.  FSYNC_PULSE_MODE
Name Bit Description
FSYNC pulse mode 0

If set, when operating in frame sync mode, the frame reading is triggered by a rising edge on the frame sync conduit.

If clear, when operating in frame sync mode, the frame reading is triggered by a rising or falling edge on the frame sync conduit (toggle mode).

Table 856.  BUFFER_N_BASE
Name Bits Description
buffer set N base address 31:0 Set this to the base address of buffer set N.
Table 857.  BUFFER_N_NUM_BUFFERS
Name Bits Description
buffer set N number of buffers 31:0 Set this to the number of buffers in set N.
Table 858.  BUFFER_N_INTER_BUFFER_OFFSET
Name Bits Description
buffer set N inter-buffer offset 31:0

Set this to the inter-buffer address increment for set N.

Usually this is equal or greater than bytes per line * BUFFER_N_HEIGHT.

Table 859.  BUFFER_N_INTER_LINE_OFFSET
Name Bits Description
buffer set N inter-line offset 31:0

Set this to the interline address increment for set N.

Usually bytes per pixel * BUFFER_N_WIDTH.

Table 860.  BUFFER_N_WIDTH
Name Bits Description
buffer set N buffer width 16:0 Set this to the width in pixels of the buffers in set N. If lite mode is off, the IP uses it also for outgoing image information packets.
Table 861.  BUFFER_N_HEIGHT
Name Bits Description
buffer set N buffer height 16:0 Set this to the height in pixels of the buffers in set N. If lite mode is off, the IP uses it also for outgoing image information packets.
Table 862.  BUFFER_N_INTERLACE
Name Bits Description
buffer set N interlace nibble 3:0 For outgoing image information packets if Lite mode is off and to set TUSER[1] if Lite mode is on.
Table 863.  BUFFER_N_COLORSPACE
Name Bits Description
buffer set N buffer colorspace 6:0 If Lite mode is off, for outgoing image information packets. Unused if Lite mode is on.
Table 864.  BUFFER_N_SUBSAMPLING
Name Bits Description
buffer set N buffer subsampling 1:0 If Lite mode is off, for outgoing image information packets. Unused if Lite mode is on.
Table 865.  BUFFER_N_COSITING
Name Bits Description
buffer set N buffer cositing 1:0 If Lite mode is off, for outgoing image information packets. Unused if Lite mode is on.
Table 866.  BUFFER_N_BPS
Name Bits Description
buffer set N buffer BPS 4:0 If Lite mode is off, for outgoing image information packets. Unused if Lite mode is on.
Table 867.  BUFFER_N_FIELD_COUNT
Name Bits Description
buffer set N starting field count 15:0 If Lite mode is off, the starting field count for outgoing image information and EOF packets. The image information and EOF field counts increment for each frame output and reset to this value after a write to COMMIT. Unused if Lite mode is on.