Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

27.2. Full Raster to Clocked Video Converter Parameters

The IP offers compile-time parameters.
Table 461.  Main Parameters
Parameter Values Description
Video Data Format
CV Bus Style Lite, CVI or CVO

Select which sideband signals the IP drives, and which signals are available in Platform Designer.

A second tab allows configuration of the CV bus style.

Bits per color sample 6 to 16 Number of bits per color sample
Number of color planes 1 to 4 Number of color planes in a pixel
Number of pixels in parallel 1, 2, 4 or 8 Number of pixels transmitted every clock
AXI4S FR Bus has tReady connection True or false

Select True so the full raster interface contains the AXI4-S tReady signal.

Select False to remove the tReady signal.

Control Settings 73
Memory-mapped control interface True or false Select True, to enable the CPU interface and associated signals. When False, the IP removes the CPU interface, and all CPU registers use default values.
Separate clock for control interface True or false

Select True to include the signal cpu_clock to Platform Designer. You can assume it to be asynchronous to the video domain.

When False, the CPU interface uses the signal vid_clock.

Figure 73. Main Parameters
Table 462.  Lite Parameters
Parameters Values Description
Parameters
Valid signal On or off When you select Lite the IP includes an optional data valid output signal, cv_vid_out_valid. Turn on to turn on this output in the IP. The Platform Designer GUI includes or removes the signal from the cv_vid_out conduit as appropriate.
Ready signal On or off When you select Lite, the IP includes an optional data ready input signal, cv_vid_out_ready. Turn on to turn on this input in the IP. Platform Designer includes or removes the signal from the cv_vid_out conduit as appropriate.
Timing signals sync, blank, or both Select which timing signals (blank timing or sync timing) are available. Platform Designer includes or removes the signals from the cv_vid_out conduit as appropriate
Figure 74. Lite Parameters
Table 463.  CVI Parameters
Parameter Allowed Range Description
CVI Core Parameters
Export the total resolution No Export or Add signals for export

The dimensions of the full raster (active and blanking) can be output from the IP as 16-bit signals.

Platform Designer includes or removes the signals from the cv_vid_out conduit as appropriate

CVI Legacy Tie Offs
Include the vid_hd_sdn signal True or False Select True to add this signal to the cv_vid_out conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the vid_std signal True or False Select True to add this signal to the cv_vid_out conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Width of vid_std 1 to 16 The width of the vid_std signal.
Include the hdmi_duplication signal True or False Select True to add this signal to the cv_vid_out conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Figure 75. CVI Parameters
Table 464.  CVO Parameters
Parameters Allowed Range Description
CVO Legacy Tie Offs
Use CV Clock True or False

Select True to add this signal to the cv_vid_out conduit.

The clock signal is an input on the cv_vid_out conduit. If you select True, the IP uses it as the internal video clock.

Include the underflow signal True or False Select True to add this signal to the cv_vid_out conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the vid_mode_change signal True or False Select True to add this signal to the cv_vid_out conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the frame lock signals True or False Select True to add this signal to the cv_vid_out conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the vid_std signal True or False Select True to add this signal to the cv_vid_out conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Width of vid_std 1 to 16 The width of the vid_std signal.
Figure 76. CVO Parameters
73 These parameters are only available when you select CVI or CVO for CV Bus Style