Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

8.1.1. 1D LUT IP Performance and Resources

Intel provides resource and utilization data for guidance only. The IP resource usage depends on the device family, compilation software version, compilation seed randomization, and other parameterization options.
Table 32.  1D LUT IP Performance and ResourcesFor 10-bit LUT and 3 Color Channels
Device Pixels in Parallel Bits per Color Sample Max Resolution ALM M20k DSP

fMAX

(MHz)

Intel Agilex 7 speed grade 2 (AGFA012R24A2E2V) 1 10 2k 969 3 3 807
1 16 2k 2,203 6 3 818
4 10 8k 3,169 12 12 803
4 16 8k 8,114 24 12 773
Intel Arria 10 speed grade 1 (10AS066H1F34E1HG) 1 10 2k 853 7 3 621
1 16 2k 1,793 28 3 546
2 10 4k 1,505 13 6 598
2 16 4k 3377 55 6 508
Intel Cyclone 10 GX speed grade 5 (10CX220YF672E5G) 1 10 2k 852 7 3 572
1 16 2k 1,788 28 3 445
Intel Stratix 10 speed grade 1 (1SX280LN2F43E1VG) 1 10 2k 1,029 3 3 705
1 16 2k 2085 7 3 674
2 10 4k 1764 6 6 675
2 16 4k 4308 13 6 691