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1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. AXI-Stream Broadcaster Intel® FPGA IP
11. Bits per Color Sample Adapter Intel FPGA IP
12. Black Level Correction Intel® FPGA IP
13. Black Level Statistics Intel® FPGA IP
14. Chroma Key Intel® FPGA IP
15. Chroma Resampler Intel® FPGA IP
16. Clipper Intel® FPGA IP
17. Clocked Video Input Intel® FPGA IP
18. Clocked Video to Full-Raster Converter Intel® FPGA IP
19. Clocked Video Output Intel® FPGA IP
20. Color Plane Manager Intel® FPGA IP
21. Color Space Converter Intel® FPGA IP
22. Defective Pixel Correction Intel® FPGA IP
23. Deinterlacer Intel® FPGA IP
24. Demosaic Intel® FPGA IP
25. FIR Filter Intel® FPGA IP
26. Frame Cleaner Intel® FPGA IP
27. Full-Raster to Clocked Video Converter Intel® FPGA IP
28. Full-Raster to Streaming Converter Intel® FPGA IP
29. Genlock Controller Intel® FPGA IP
30. Generic Crosspoint Intel® FPGA IP
31. Genlock Signal Router Intel® FPGA IP
32. Guard Bands Intel® FPGA IP
33. Histogram Statistics Intel® FPGA IP
34. Interlacer Intel® FPGA IP
35. Mixer Intel® FPGA IP
36. Pixels in Parallel Converter Intel® FPGA IP
37. Scaler Intel® FPGA IP
38. Stream Cleaner Intel® FPGA IP
39. Switch Intel® FPGA IP
40. Tone Mapping Operator Intel® FPGA IP
41. Test Pattern Generator Intel® FPGA IP
42. Unsharp Mask Intel® FPGA IP
43. Video and Vision Monitor Intel FPGA IP
44. Video Frame Buffer Intel® FPGA IP
45. Video Frame Reader Intel FPGA IP
46. Video Frame Writer Intel FPGA IP
47. Video Streaming FIFO Intel® FPGA IP
48. Video Timing Generator Intel® FPGA IP
49. Vignette Correction Intel® FPGA IP
50. Warp Intel® FPGA IP
51. White Balance Correction Intel® FPGA IP
52. White Balance Statistics Intel® FPGA IP
53. Design Security
54. Document Revision History for Video and Vision Processing Suite User Guide
29.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
29.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
29.4.3. Setting the VCXO hold over
29.4.4. Restarting the Genlock Controller IP
29.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
29.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
29.4.7. Disturbing a Reference Clock (a cable pull)
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43.3. Video and Vision Monitor IP Functional Description
When using the full variant of the Intel FPGA Streaming Video interface protocol, the Video and Vision Monitor IP searches the incoming video stream for image information packets. The IP decodes the image information packets and then produces the contents of the last image information packet that you receive via the register map. The Image Information packets also specify the expected resolution for each incoming video frame. The IP counts the number of pixels in each line and the number of lines in each frame. Based on the values of these counters and the expected frame size, the IP keeps a count of the number of frames that match and do not match their expected sizes. The IP also counts the number of frames for which the following end-of-field packets assert their broken frame flag. The IP reports all these values to you via the register map. You can also reset the frame counts at any time by writing to an address in the register map.
Lite variants of the Intel FPGA Streaming Video interface protocol have no image information packets in the incoming stream to provide details of the expected frame size. You must supply this information via the register map. Lite variants also have no end-of-field packets, so this counter is not when Lite mode is on. Other than these differences, the behavior of the IP is the same as with the full variant of the protocol.
When the IP and its interfaces are parameterized for a single pixel in parallel, the IP can count the exact number of pixels in each line. The Intel FPGA Streaming Video protocol does not indicate that any of the pixels are unused on the final data beat of each packet when interfaces are parameterized for multiple pixels in parallel. Therefore, the IP cannot exactly count the number of pixels in each line when the number of pixels in parallel is greater than 1. It can count the number of beats of data in the packet and, based on this value, provide an upper and lower bound on the number of pixels.
pixels_in_parallel x (data_beats-1) + 1 <= number_of_pixels <= pixels_in_parallel x data_beats
The IP reports two-line length values to the register map:
- The minimum number of pixels in any line packet for the most recent frame, taken from the lower bound count of the number of pixels for each line.
- The maximum number of pixels in any line packet for the most recent frame, taken from the upper bound count of the number of pixels for each line.
If the IP is parameterized for 1 pixel in parallel, for frames that match their specified dimensions both these reported width values match the specified width. If the IP is parameterized for multiple pixels in parallel, the maximum and minimum line lengths have different values but adhere to the following constraints for frames that match their sizes.
expected_width – pixels_in_parallel < minimum_width <= expected_width
expected_width <= maximum_width < expected_width + pixels_in_parallel
The IP checks these constraints when deciding if each frame has to match its expected dimensions.