Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

44.4. Video Frame Buffer IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 797.  Video Frame Buffer IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_VIDEO FRAME BUFFER as appropriate and with an optional REG suffix
Address Register Access Description
Lite 118 Full
Parameterization registers
0x0000 VID_PID RO RO Read this register for the Video Frame Buffer product ID. This register always returns 0x6AF7_0237.
0x0004 VERSION RO RO Read this register for the IP version information.
0x0008 LITE_MODE RO RO

Read this register to determine if Lite mode is on or off.

This register returns 0 when Lite mode is off and 1 when on.

0x000C DEBUG_ENABLED RO RO Read this register to determine if Debug features is on.
0x0010 MAX_WIDTH RO RO Read this register to determine the maximum supported frame width.
0x0014 MAX_HEIGHT RO RO Read this register to determine the maximum supported frame height.
0x0018 DROP_ENABLED RO RO Read this register to see if Enable dropping of input frames is on.
0x001C REPEAT_ENABLED RO RO Read this register to see if Enable repeating of output frames is on.
0x0020 INVALID_FRAMES_DROPPED RO RO Read this register to see if Enable the dropping of broken frames at the input is on.
0x0024 MEM_BASE_ADDR RO RO Read this register for the base address of stored frames in memory.
0x0028 MEM_BUFFER_STRIDE RO RO Read this register for the buffer stride in memory.
0x002C MEM_LINE_STRIDE RO RO Read this register for the line stride in memory.
0x0030 BPS RO RO Read this register for the number of bits per symbol configured.
0x0034 NUMBER_OF_COLOR_PLANES RO RO Read this register for the number of color planes.
0x0038 PIXELS_IN_PARALLEL RO RO Read this register for the number of pixels in parallel.
0x003C PACKING RO RO Read this register for the pixel packing scheme.
0x0040to 0x011F Unused.
Control and Debug registers

For more details about these registers, refer to Control Packets

0x0120 IMG_INFO_WIDTH RW RO When you turn on lite mode, the expected width of the incoming video fields. When you turn off lite mode, the received width in the IP derives from the image information packets.
0x0124 IMG_INFO_HEIGHT RW RO When you turn on lite mode, the expected height of the incoming video fields. When you turn off lite mode, the received height in the IP derives from the image information packets.
0x0128 IMG_INFO_INTERLACE RW RO When you turn on lite mode, the expected interlace information of the incoming video fields. When you turn off lite mode, the received interlace information in image information packets.
0x012C RESERVED RW RO Unused.
0x0130 IMG_INFO_COLORSPACE RW RO When you turn on lite mode, the expected color space of the incoming video fields. When you turn off lite mode, the received color space in image information packets.
0x0134 IMG_INFO_SUBSAMPLING RW RO When you turn on lite mode, the expected chroma subsampling of the incoming video fields. When you turn off lite mode, the received chroma subsampling in image information packets.
0x0138 IMG_INFO_COSITING RW RO When you turn on lite mode, the expected chroma co-siting of the incoming video fields. When you turn off lite mode, the received chroma co-siting in image information packets.
0x013C IMG_INFO_FIELD_COUNT - RO The received field count field in image information packets.
0x0140 INPUT_STATUS RO RO

Bit 0 input status bit.

1 = Video Frame Buffer is receiving and processing a video field, 0 otherwise.

0x0144 NUM_INPUT_FIELDS RO RO Read this register for a 32 bit count of frames received. The counter still increments if the frame is subsequently dropped.
0x0148 NUM_DROPPED_FIELDS RO RO Read this register for a 32 bit count of frames dropped.
0x014C NUM_INVALID_FIELDS RO RO Read this register for a 32 bit count of invalid frames received.
0x0150 OUTPUT_STATUS RO RO

Bit 0: output status bit.

1 = Video Frame Buffer is outputting a video field, 0 otherwise.

Bit 1: AUX FIFO overflow bit

1 = Auxiliary FIFO is overflowing, 0 otherwise. Reset the video frame buffer to reset this bit.

0x0154 NUM_OUTPUT_FIELDS RO RO Read this register for a 32-bit count of frames output. The counter increments for frame repeats.
0x0158 NUM_REPEATED_FIELDS RO RO Read this register for a 32-bit count of repeated frames.
0x015C OUTPUT_CONTROL RW RW

Write a 1 to this register for the frame buffer to start producing buffered frames.

Write a 0 to this register for the frame buffer to stop producing buffered frames.

Register Bit Descriptions

Table 798.  VID_PID
Name Bits Description
Frame buffer version ID and product ID 31:0 This register always returns 0x6AF7_0237
  • 15:0 is the product ID and always returns 0x0237
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 799.  VERSION
Name Bits Description
Register map version 7:0 Register map version.
IP patch revision 15:8 -
IP update revision 23:16 Updated when the IP version changes.
IP major revision 31:24 Updated when the IP version changes.
Table 800.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 0 Returns 1 if you turn on lite mode.
Unused 31:1 Unused.
Table 801.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 0 Returns 1 if you turn on Debug features.
Unused 31:1 Unused.
Table 802.  MAX_WIDTH
Name Bits Description
Max width 31:0 This register returns the maximum supported frame width.
Table 803.  MAX_HEIGHT
Name Bits Description
Max height 31:0 This register returns the maximum supported frame height.
Table 804.  DROP_ENABLED
Name Bits Description
Drop enabled 0 This register returns 1 if Enable dropping of input frames is on and 0 if it is off.
Table 805.  REPEAT_ENABLED
Name Bits Description
Repeat enabled 0 This register returns 1 if Enable repeating of output frames is on and 0 if it is off.
Table 806.  INVALID_FRAMES_DROPPED
Name Bits Description
Invalid frames dropped 0 This register returns 1 if Enable the dropping of broken frames at the input and 0 if it is off.
Table 807.  MEM_BASE_ADDR
Name Bits Description
Mem base address 31:0 This register returns the base address of stored frames in memory.
Table 808.  MEM_BUFFER_STRIDE
Name Bits Description
Mem buffer stride 31:0 This register returns the buffer stride in memory.
Table 809.  MEM_LINE_STRIDE
Name Bits Description
Mem line stride 31:0 This register returns the line stride in memory.
Table 810.  BPS
Name Bits Description
BPS 31:0 This register returns the number of bits per symbol.
Table 811.  NUMBER_OF_COLOR_PLANES
Name Bits Description
Number of color planes 31:0 This register returns the number of color planes.
Table 812.  PIXELS_IN_PARALLEL
Name Bits Description
Pixels in parallel 31:0 This register returns the number of pixels in parallel.
Table 813.  PACKING
Name Bits Description
Packing 31:0

This register returns the packing scheme:

0 = Perfect packing

1 = Color packing

2 = Pixel packing

Table 814.  IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When you turn on lite mode, write to this register to set the expected width of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register uses the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 815.  IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When you turn on lite mode, write to this register to set the expected height of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 816.  IMG_INFO_INTERLACE
Name Bits Description
Interlace Nibble bits 3:0

When you turn on lite mode, write to this register to set the expected interlacing of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the intlaceNibble field from the most recently received image information packet.

unused 31:4 Unused.
Table 817.  IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

When you turn on lite mode, write to this register to set the expected color space of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit CSP field from the most recently received image information packet.

unused 31:7 Unused.
Table 818.  IMG_INFO_SUBSAMPLING
Name Bits Description
CSPSubSa code bits 1:0

When you turn on lite mode, write to this register to set the expected chroma subsampling of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 819.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

When you turn on lite mode, write to this register to set the expected chroma co-siting of the incoming video fields.

When you turn off lite mode and turn on Debug features, this register returns the COSITEfield from the most recently received image information packet.

unused 31:2 Unused.
Table 820.  IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0

When you turn on lite mode, this register has no function.

When you turn off lite mode and turn on Debug features, this register returns the 7 bit

FIELD_COUNT field from the most recently received image information packet.

unused 31:7 Unused.
Table 821.  INPUT_STATUS
Name Bits Description
Status bit 0 1= Video Frame Buffer is receiving and processing a video field, 0 otherwise.
Table 822.  NUM_INPUT_FIELDS
Name Bits Description
NUM_INPUT_FIELDS 31:0 Read this register for a 32 bit count of frames received. The counter still increments if the frame is subsequently dropped.
Table 823.  NUM_DROPPED_FIELDS
Name Bits Description
NUM_DROPPED_FIELDS 15:0 Read these bits for a count of frames dropped
Table 824.  NUM_INVALID_FIELDS
Name Bits Description
NUM_INVALID_FIELDS 31:0 Read these bits for a count of invalid frames received
Table 825.   OUTPUT_STATUS
Name Bits Description
OUTPUT_STATUS 0

Bit 0: output status bit.

1 = Video Frame Buffer is outputting a video field, 0 otherwise.

Bit 1: AUX FIFO overflow bit

1 = Aux FIFO is overflowing, 0 otherwise. Reset the video frame buffer to reset this bit.

Table 826.   NUM_OUTPUT_FIELDS
Name Bits Description
NUM_OUTPUT_FIELDS 31:0 Read these bits for a count of frames output. The counter also increments for frame repeats.
Table 827.  NUM_REPEATED_FIELDS
Name Bits Description
NUM_REPEATED_FIELDS 31:0 Read these bits for a count of repeated frames. Subtract this value from NUM_OUTPUT_FIELDS to determine how many frames the IP produces once only.
Table 828.  OUTPUT_CONTROL
Name Bits Description
OUTPUT_CONTROL BIT 0

Write a 1 to this register for the frame buffer to start outputting buffered frames.

Write a 0 to this register for the frame buffer to stop producing buffered frames.

118

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.