Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 5/08/2024
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide

40.1.2. TMO IP Performance and Resource Utilization

Intel provides resource and utilization data for guidance. TMO IP resource utilization depends on the device family and the number of supported bits per sample and pixels in parallel.
Table 703.  Resource Utilization for Agilex™ 7 DevicesTargeting Agilex™ 7 AGIB027R29A1E1V device
Parameters Resource Utilization

Bits per Sample

Pixels in Parallel

ALMs M20Ks DSP Blocks
8 1 7,796 53 56
8 2 11,560 79 105
8 4 18,141 130 203
10 1 7,812 53 56
10 2 11,718 79 105
10 4 18,7979 132 203
12 1 8,034 56 56
12 2 11,881 85 105
12 4 19,998 144 203
Table 704.  Resource Utilization for Intel Arria 10 DevicesTargeting Intel Arria 10 10AS066H1F34E1HG device.
Parameters Resource Utilization

Bits per Sample

Pixels in Parallel

ALMs M20Ks DSP Blocks
8 1 6,396 64 56
8 2 9,051 99 105
8 4 14,330 164 203
10 1 6,536 64 56
10 2 9,287 99 105
10 4 14,787 167 203
12 1 6,628 67 56
12 2 9,569 105 105
12 4 15,249 181 203
Table 705.  Resource Utilization for Intel Cyclone 10 GX DevicesTargeting Intel Cyclone 10 GX 10CX220YF672E5G device
Parameters Resource Utilization

Bits per Sample

Pixels in Parallel

ALMs M20Ks DSP Blocks
8 1 6,437 64 56
8 2 9,076 99 105
10 1 6,539 64 56
10 2 9,313 99 105
12 1 6,662 67 56
12 2 9,543 105 105
Table 706.  Resource Utilization for Intel Stratix 10 DevicesTargeting Intel Stratix 10 1SX280LN2F43E1VG device
Parameters Resource Utilization

Bits per Sample

Pixels in Parallel

ALMs M20Ks DSP Blocks
8 1 7,921 53 56
8 2 11,466 79 105
8 4 18,079 130 203
10 1 8,087 53 56
10 2 11,482 79 105
10 4 18,663 132 203
12 1 8,317 56 56
12 2 12,349 85 105
12 4 18,746 144 203