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1.1.1. Timing Path and Clock Analysis
1.1.2. Clock Setup Analysis
1.1.3. Clock Hold Analysis
1.1.4. Recovery and Removal Analysis
1.1.5. Multicycle Path Analysis
1.1.6. Metastability Analysis
1.1.7. Timing Pessimism
1.1.8. Clock-As-Data Analysis
1.1.9. Multicorner Timing Analysis
1.1.10. Time Borrowing
2.1. Using Timing Constraints throughout the Design Flow
2.2. Timing Analysis Flow
2.3. Applying Timing Constraints
2.4. Timing Constraint Descriptions
2.5. Timing Report Descriptions
2.6. Scripting Timing Analysis
2.7. Using the Quartus® Prime Timing Analyzer Document Revision History
2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4.4.5.1. Default Multicycle Analysis
2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset
2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5.1. Report Fmax Summary
2.5.2. Report Timing
2.5.3. Report Timing By Source Files
2.5.4. Report Data Delay
2.5.5. Report Net Delay
2.5.6. Report Clocks and Clock Network
2.5.7. Report Clock Transfers
2.5.8. Report Metastability
2.5.9. Report CDC Viewer
2.5.10. Report Asynchronous CDC
2.5.11. Report Logic Depth
2.5.12. Report Neighbor Paths
2.5.13. Report Register Spread
2.5.14. Report Route Net of Interest
2.5.15. Report Retiming Restrictions
2.5.16. Report Register Statistics
2.5.17. Report Pipelining Information
2.5.18. Report Time Borrowing Data
2.5.19. Report Exceptions and Exceptions Reachability
2.5.20. Report Bottlenecks
2.5.21. Check Timing
2.5.22. Report SDC
3.1.1. CDC Timing Overview
3.1.2. Identifying CDC Timing Issues Using Design Assistant
3.1.3. Identifying CDC Timing Issues Using Timing Reports
3.1.4. Debug CDC Example 1—Incorrect SDC Definition
3.1.5. Debug CDC Example 2—Additional Logic in the Crossing
3.1.6. Debug CDC Example 3—CDC Depending on Two Simultaneous Clock Domains
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2.2.3.1. Running Post-Synthesis Early Timing Analysis
Running the Early Timing Analysis stage of compilation provides a preliminary view of your design's core timing. Before running Early Timing Analysis, you must setup your design RTL, the Quartus® Prime project, specify timing constraints, and run the Compiler through the Analysis & Synthesis stage.
To run post-synthesis Early Timing Analysis, follow these steps:
- Specify SDC-on-RTL timing constraints for Early Timing Analysis, as Specifying SDC-on-RTL Timing Constraints describes.
Note: As an alternative to SDC-on-RTL, you can define a synthesis-only .sdc, as Specifying Synthesis-Only SDC Timing Constraints describes.
- On the Compilation Dashboard, click Analysis & Elaboration. Analysis & Elaboration processes all SDC-on-RTL, applying the constraints to the design netlist. During Analysis & Elaboration, messages confirm that the Compiler appropriately applies each .rtlsdc file according to its assigned module.
- To review the implementation of constraints when Elaboration & Analysis completes, click the Open Compilation Reports icon next to Elaboration & Analysis in the Compilation Dashboard.
- Click the SDC Constraints > SDC-on-RTL File List report to view all SDC-on-RTL files in the current project.
Figure 42. SDC-on-RTL File List Report
- Click Analysis & Synthesis on the Compilation Dashboard. Analysis & Synthesis transforms the elaborated netlist into a node netlist for device resource mapping and generates a simplified device delay model that excludes precise Fitter-generated timing delays. This simplified delay model provides an early overview of the design delays based on block types that connect to a net. Analysis & Synthesis propagates SDC-on-RTL constraints to subsequent compilation stages, thereby applying to all subsequent Timing Analyzer runs.
- To run Early Timing Analysis and view the results, double-click Early Timing Analysis on the Compilation Dashboard. The Compiler runs Analysis & Synthesis and then initializes the Timing Analyzer.
Figure 43. Running Early Timing Analysis from Compilation Dashboard
- When Analysis & Synthesis completes, click the Open Timing Analyzer icon next to Early Timing Analysis on the Compilation Dashboard. The Timing Analyzer opens with the updated timing netlist loaded automatically.
- In the Timing Analyzer reports, view the preliminary timing report data measured against your SDC-on-RTL constraints, such as the Setup Summary, Create Generated Clocks, and Set False Path reports. Refer to Step 4: Analyze Timing Reports.