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1.1.1. Timing Path and Clock Analysis
1.1.2. Clock Setup Analysis
1.1.3. Clock Hold Analysis
1.1.4. Recovery and Removal Analysis
1.1.5. Multicycle Path Analysis
1.1.6. Metastability Analysis
1.1.7. Timing Pessimism
1.1.8. Clock-As-Data Analysis
1.1.9. Multicorner Timing Analysis
1.1.10. Time Borrowing
2.1. Using Timing Constraints throughout the Design Flow
2.2. Timing Analysis Flow
2.3. Applying Timing Constraints
2.4. Timing Constraint Descriptions
2.5. Timing Report Descriptions
2.6. Scripting Timing Analysis
2.7. Using the Quartus® Prime Timing Analyzer Document Revision History
2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4.4.5.1. Default Multicycle Analysis
2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset
2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5.1. Report Fmax Summary
2.5.2. Report Timing
2.5.3. Report Timing By Source Files
2.5.4. Report Data Delay
2.5.5. Report Net Delay
2.5.6. Report Clocks and Clock Network
2.5.7. Report Clock Transfers
2.5.8. Report Metastability
2.5.9. Report CDC Viewer
2.5.10. Report Asynchronous CDC
2.5.11. Report Logic Depth
2.5.12. Report Neighbor Paths
2.5.13. Report Register Spread
2.5.14. Report Route Net of Interest
2.5.15. Report Retiming Restrictions
2.5.16. Report Register Statistics
2.5.17. Report Pipelining Information
2.5.18. Report Time Borrowing Data
2.5.19. Report Exceptions and Exceptions Reachability
2.5.20. Report Bottlenecks
2.5.21. Check Timing
2.5.22. Report SDC
3.1.1. CDC Timing Overview
3.1.2. Identifying CDC Timing Issues Using Design Assistant
3.1.3. Identifying CDC Timing Issues Using Timing Reports
3.1.4. Debug CDC Example 1—Incorrect SDC Definition
3.1.5. Debug CDC Example 2—Additional Logic in the Crossing
3.1.6. Debug CDC Example 3—CDC Depending on Two Simultaneous Clock Domains
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2.2.3.2. Running Post-Fit Timing Analysis
Before running post-fit timing analysis, you must run the Fitter to apply conventional SDC constraints to the post-fit timing netlist. The Fitter then attempts to place the logic of your design to adhere to the timing constraints you specify. After running the Fitter, the Timing Analyzer generates reports detailing the margin (slack) by which your design either meets or fails each constraint. The post-fit timing netlist accounts for actual path delays.
To run post-fit timing analysis, follow these steps:
- Specify conventional SDC timing constraints for post-fit timing analysis, as Specifying Conventional SDC Timing Constraints describes.
- On the Compilation Dashboard, run any stage of the Fitter (Plan, Place, Route, Retime, Fitter (Finalize)) or run a full compilation.
Figure 44. Fitter Stages in Compilation Dashboard
- When the Fitter completes, click the Timing Analyzer icon next to the completed stage in the Compilation Dashboard. The Setup Summary report opens by default in the Timing Analyzer.
- Review the timing reports. To generate additional timing reports for analysis, click the Reports menu, and then click one of the submenu items to generate that report, as Step 4: Analyze Timing Reports describes.
Figure 45. Setup Summary Report
- To run timing analysis under different operation conditions, click Set Operating Conditions on the Tasks pane and specify options, as Setting the Operating Conditions for Timing Analysis describes. By default, the Timing Analyzer generates reports for all supported operating conditions.
- If you specify any settings or constraints that impact timing analysis, click Update Timing Netlist on the Tasks pane to apply the new constraints to the timing netlist.