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1.2.1. Timing Path and Clock Analysis
1.2.2. Clock Setup Analysis
1.2.3. Clock Hold Analysis
1.2.4. Recovery and Removal Analysis
1.2.5. Multicycle Path Analysis
1.2.6. Metastability Analysis
1.2.7. Timing Pessimism
1.2.8. Clock-As-Data Analysis
1.2.9. Multicorner Timing Analysis
1.2.10. Time Borrowing
2.1. Using Timing Constraints throughout the Design Flow
2.2. Timing Analysis Flow
2.3. Applying Timing Constraints
2.4. Timing Constraint Descriptions
2.5. Timing Report Descriptions
2.6. Scripting Timing Analysis
2.7. Using the Quartus® Prime Timing Analyzer Document Revision History
2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4.4.5.1. Default Multicycle Analysis
2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset
2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5.1. Report Fmax Summary
2.5.2. Report Timing
2.5.3. Report Timing By Source Files
2.5.4. Report Data Delay
2.5.5. Report Net Delay
2.5.6. Report Clocks and Clock Network
2.5.7. Report Clock Transfers
2.5.8. Report Metastability
2.5.9. Report CDC Viewer
2.5.10. Report Asynchronous CDC
2.5.11. Report Logic Depth
2.5.12. Report Neighbor Paths
2.5.13. Report Register Spread
2.5.14. Report Route Net of Interest
2.5.15. Report Retiming Restrictions
2.5.16. Report Register Statistics
2.5.17. Report Pipelining Information
2.5.18. Report Time Borrowing Data
2.5.19. Report Exceptions and Exceptions Reachability
2.5.20. Report Bottlenecks
2.5.21. Check Timing
2.5.22. Report SDC
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2.2.2.1. Specifying SDC-on-RTL Timing Constraints
To specify SDC-on-RTL timing constraints for post-synthesis Early Timing Analysis, follow these steps:
- In the Quartus® Prime software, click File > New and then select the SDC File Targeting RTL Names (.rtlsdc) file type. The new file opens in the Text Editor.
You can specify any extension for SDC-on-RTL constraints, but this document always uses the file extension .rtlsdc to distinguish from conventional SDC files.
- In the Text Editor, define SDC-on-RTL constraints. You can click Edit > Insert Template > Timing Analyzer to insert available SDC templates. Alternatively, use any other text editor to enter the constraints and save as .rtlsdc file type.
Note: SDC-on-RTL constraints support a subset of conventional SDC commands. The syntax and arguments of SDC-on-RTL constraints aligns with the SDC 2.1 standard. The Quartus Prime software may support more than just the SDC 2. 1 commands because of some Quartus Prime software-specific arguements.Figure 39. Inserting SDC Templates
Note: The -comment argument in SDC-on-RTL allows you to add a constraint comment. This comment does not appear in timing analysis reports. - Save the .rtlsdc file in the Quartus® Prime Text Editor, turning on the Add File to Project option.
Note: You can add any SDC file to the project at any time by clicking Assignments > Settings > Timing Analyzer.
- Run post-synthesis Early Timing Analysis, as Running Post-Synthesis Early Timing Analysis describes.
Note: As an alternative to SDC-on-RTL constraints, you can consider initially specifying synthesis-only constraints that apply only to the Analysis & Synthesis stage of compilation, as Specifying Synthesis-Only SDC Timing Constraints describes.