Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 4/01/2024
Public
Document Table of Contents

2.2.2.3. Specifying Synthesis-Only SDC Timing Constraints

You use this synthesis-only SDCs if you want to create custom SDC's that apply just for post-synthesis timing analysis, but you do not want the constraints to apply to other downstream stages of the compilation flow. If you want the constraints to persist post-synthesis, you can use SDC-on-RTL constraints, as Specifying SDC-on-RTL Timing Constraints describes.

Follow these steps to define a conventional .sdc file that applies only to the Analysis & Synthesis stage of compilation.
  1. Create a conventional .sdc file that contains only the timing constraints for the Analysis & Synthesis stage of compilation, as Specifying Conventional SDC Timing Constraints describes.
  2. To apply the conventional .sdc to the project for synthesis-only, add the following assignment to the project:
    set_global_assignment -name SDC_ENTITY_FILE <file>.sdc /
       -entity <name> -read_during_post_syn_and_not_post_fit_timing_analysis
  3. To run design synthesis and apply the constraints to the timing netlist, click Analysis & Synthesis on the Compilation Dashboard.
  4. Click the Open Timing Analyzer icon next to Analysis & Synthesis on the Compilation Dashboard. The synthesis-only constraints now apply to only the static timing analysis of this synthesized snapshot.
  5. Analyze the results of Early Timing Analysis, as Step 4: Analyze Timing Reports describes.