Visible to Intel only — GUID: onc1707776499549
Ixiasoft
1.2.1. Timing Path and Clock Analysis
1.2.2. Clock Setup Analysis
1.2.3. Clock Hold Analysis
1.2.4. Recovery and Removal Analysis
1.2.5. Multicycle Path Analysis
1.2.6. Metastability Analysis
1.2.7. Timing Pessimism
1.2.8. Clock-As-Data Analysis
1.2.9. Multicorner Timing Analysis
1.2.10. Time Borrowing
2.1. Using Timing Constraints throughout the Design Flow
2.2. Timing Analysis Flow
2.3. Applying Timing Constraints
2.4. Timing Constraint Descriptions
2.5. Timing Report Descriptions
2.6. Scripting Timing Analysis
2.7. Using the Quartus® Prime Timing Analyzer Document Revision History
2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4.4.5.1. Default Multicycle Analysis
2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset
2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5.1. Report Fmax Summary
2.5.2. Report Timing
2.5.3. Report Timing By Source Files
2.5.4. Report Data Delay
2.5.5. Report Net Delay
2.5.6. Report Clocks and Clock Network
2.5.7. Report Clock Transfers
2.5.8. Report Metastability
2.5.9. Report CDC Viewer
2.5.10. Report Asynchronous CDC
2.5.11. Report Logic Depth
2.5.12. Report Neighbor Paths
2.5.13. Report Register Spread
2.5.14. Report Route Net of Interest
2.5.15. Report Retiming Restrictions
2.5.16. Report Register Statistics
2.5.17. Report Pipelining Information
2.5.18. Report Time Borrowing Data
2.5.19. Report Exceptions and Exceptions Reachability
2.5.20. Report Bottlenecks
2.5.21. Check Timing
2.5.22. Report SDC
Visible to Intel only — GUID: onc1707776499549
Ixiasoft
2.2.2.3. Specifying Synthesis-Only SDC Timing Constraints
You use this synthesis-only SDCs if you want to create custom SDC's that apply just for post-synthesis timing analysis, but you do not want the constraints to apply to other downstream stages of the compilation flow. If you want the constraints to persist post-synthesis, you can use SDC-on-RTL constraints, as Specifying SDC-on-RTL Timing Constraints describes.
Follow these steps to define a conventional .sdc file that applies only to the Analysis & Synthesis stage of compilation.
- Create a conventional .sdc file that contains only the timing constraints for the Analysis & Synthesis stage of compilation, as Specifying Conventional SDC Timing Constraints describes.
- To apply the conventional .sdc to the project for synthesis-only, add the following assignment to the project:
set_global_assignment -name SDC_ENTITY_FILE <file>.sdc / -entity <name> -read_during_post_syn_and_not_post_fit_timing_analysis
- To run design synthesis and apply the constraints to the timing netlist, click Analysis & Synthesis on the Compilation Dashboard.
- Click the Open Timing Analyzer icon next to Analysis & Synthesis on the Compilation Dashboard. The synthesis-only constraints now apply to only the static timing analysis of this synthesized snapshot.
- Analyze the results of Early Timing Analysis, as Step 4: Analyze Timing Reports describes.