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1.1. Compilation Overview
1.2. Using the Node Finder
1.3. Design Analysis & Elaboration
1.4. Design Synthesis
1.5. Design Place and Route
1.6. Incremental Optimization Flow
1.7. Fast Forward Compilation Flow
1.8. Full Compilation Flow
1.9. HSSI Dual Simplex IP Generation Flow
1.10. Exporting Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Synthesis Language Support
1.15. Synthesis Settings Reference
1.16. Fitter Settings Reference
1.17. Design Compilation Revision History
1.4.3.1. Registering the SDC-on-RTL SDC File
1.4.3.2. Applying the SDC-on-RTL Constraints
1.4.3.3. Inspecting SDC-on-RTL Constraints
1.4.3.4. Creating Constraints in SDC-on-RTL SDC Files
1.4.3.5. Using Entity-Based SDC-on-RTL Constraints
1.4.3.6. Types of SDC Files Used in the Quartus® Prime Software
1.4.3.7. Example: Using SDC-on-RTL Features
1.10.1. Exporting a Version-Compatible Compilation Database
1.10.2. Importing a Version-Compatible Compilation Database
1.10.3. Creating a Design Partition
1.10.4. Exporting a Design Partition
1.10.5. Reusing a Design Partition
1.10.6. Viewing Quartus Database File Information
1.10.7. Clearing Compilation Results
1.12.1. Compiler Optimization Modes
1.12.2. Precompiled Component (PCC) Generation Stage
1.12.3. Compilation on a Compute Farm
1.12.4. Allow Register Retiming
1.12.5. Automatic Gated Clock Conversion
1.12.6. Enable Intermediate Fitter Snapshots
1.12.7. Fast Preserve Option
1.12.8. Fractal Synthesis Optimization
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
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1. Design Compilation
The Quartus® Prime Compiler synthesizes, places, and routes your design before generating device programming files. The Compiler supports a variety of high-level, HDL, and schematic design entry methods. The modules of the Compiler include IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and Assembler.
Compilation Dashboard
The Quartus® Prime Pro Edition version of the Compiler supports these advanced features:
- Supports Agilex™ 7, Agilex™ 5, Stratix® 10, Arria® 10, and Cyclone® 10 GX devices.
- Incremental Fitter optimization—analyze and optimize after each Fitter stage to maximize performance and shorten total compilation time.
- Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation for the highest performance in Stratix® 10 and all Agilex™ family devices.
- Partial Reconfiguration—dynamic reconfiguration of a portion of the FPGA, while the remaining FPGA continues to function.
- Block-Based Design Flows—preservation and reuse of design blocks.
Section Content
Compilation Overview
Using the Node Finder
Design Analysis & Elaboration
Design Synthesis
Design Place and Route
Incremental Optimization Flow
Fast Forward Compilation Flow
Full Compilation Flow
HSSI Dual Simplex IP Generation Flow
Exporting Compilation Results
Integrating Other EDA Tools
Compiler Optimization Techniques
Compilation Monitoring Mode
Synthesis Language Support
Synthesis Settings Reference
Fitter Settings Reference
Design Compilation Revision History