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1.1. Compilation Overview
1.2. Using the Node Finder
1.3. Design Analysis & Elaboration
1.4. Design Synthesis
1.5. Design Place and Route
1.6. Incremental Optimization Flow
1.7. Fast Forward Compilation Flow
1.8. Full Compilation Flow
1.9. HSSI Dual Simplex IP Generation Flow
1.10. Exporting Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Synthesis Language Support
1.15. Synthesis Settings Reference
1.16. Fitter Settings Reference
1.17. Design Compilation Revision History
1.4.3.1. Registering the SDC-on-RTL SDC File
1.4.3.2. Applying the SDC-on-RTL Constraints
1.4.3.3. Inspecting SDC-on-RTL Constraints
1.4.3.4. Creating Constraints in SDC-on-RTL SDC Files
1.4.3.5. Using Entity-Based SDC-on-RTL Constraints
1.4.3.6. Types of SDC Files Used in the Quartus® Prime Software
1.4.3.7. Example: Using SDC-on-RTL Features
1.10.1. Exporting a Version-Compatible Compilation Database
1.10.2. Importing a Version-Compatible Compilation Database
1.10.3. Creating a Design Partition
1.10.4. Exporting a Design Partition
1.10.5. Reusing a Design Partition
1.10.6. Viewing Quartus Database File Information
1.10.7. Clearing Compilation Results
1.12.1. Compiler Optimization Modes
1.12.2. Precompiled Component (PCC) Generation Stage
1.12.3. Compilation on a Compute Farm
1.12.4. Allow Register Retiming
1.12.5. Automatic Gated Clock Conversion
1.12.6. Enable Intermediate Fitter Snapshots
1.12.7. Fast Preserve Option
1.12.8. Fractal Synthesis Optimization
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
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1.1. Compilation Overview
The Compiler is modular, allowing you to run only the stage of compilation that you need. Each Compiler stage performs a specific function in the full compilation process. When you run any stage, the Compiler automatically runs any prerequisite stages and generates detailed reports for each stage. The Compiler can preserve a "snapshot" of the compilation results after each stage.
Compiler Stage | Description |
---|---|
IP Generation | Identifies the status and version of IP components in the project, reports outdated IP that require upgrade, and generates Intel FPGA IPs in the project. |
Analysis & Synthesis |
|
Early Timing Analysis | Combines Synopsys* Design Constraint (SDC) on RTL and post-synthesis static timing analysis. The SDC-on-RTL allows you to integrate SDC constraints that target nodes using the same names as in your RTL design early in the compilation flow and uses them in the later stages of the Quartus® Prime compilation. However, you can run the module even without RTL SDCs where you can view the synthesized timing netlist. |
Fitter (Place & Route) | Assigns the placement and routing of the design to specific device resources, while honoring timing and placement constraints. The Fitter includes the following stages:
|
Timing Analysis | Analyzes and validates the timing performance of all design logic with the Timing Analyzer. |
Power Analysis | Optional module that estimates device power consumption. Specify the electrical standard on each I/O cell and the board trace model on each I/O standard in your design. |
Assembler | Converts the Fitter's placement and routing assignments into a programming image for the FPGA device. |
EDA Netlist Writer | Generates output files for use in other EDA tools, as Integrating Other EDA Tools describes. |
Compiler Stage | Description | Available For |
---|---|---|
HSSI Dual Simplex IP Generation | A sub-stage of IP Generation that generates the dual simplex IP in your design. You can run this stage after using the Dual Simplex (DS) Assignment Editor to place supported simplex transceiver-based IPs in the same transceiver channel. Refer to HSSI Dual Simplex IP Generation Flow and the GTS Transceiver PHY User Guide. | Agilex™ 5 designs with dual simplex IP only. |
Support-Logic Generation | Compiler stage preceding Analysis & Synthesis that includes the following sub-stages:
|
Agilex™ 7 F-Tile designs only |
Retime | A sub-stage of Fitter that moves (retimes) existing registers into Hyper-Registers for fine-grained performance improvement. The "retimed" snapshot preserves the stage results. | Stratix® 10 and Agilex™ family devices only. |
Fast Forward Timing Closure Recommendations | Generates detailed reports that estimate performance gains achievable by making specific RTL modifications. Refer to Intel Hyperflex Architecture High-Performance Design Handbook | Stratix® 10 and Agilex™ family devices only. |
Each successive release of the Quartus® Prime software typically includes:
- Added support for new features in supported FPGA devices.
- Added support for new devices.
- Efficiency and performance improvements.
- Improvements to compilation time and resource use of the design software.
Due to these improvements, different versions of the Quartus® Prime Pro Edition, Quartus® Prime Standard Edition, and Quartus® Prime Lite Edition software can produce different programming files from release to release.