Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Design Analysis & Elaboration 1.3. Design Synthesis 1.4. Design Place and Route 1.5. Incremental Optimization Flow 1.6. Fast Forward Compilation Flow 1.7. Full Compilation Flow 1.8. HSSI Dual Simplex IP Generation Flow 1.9. Exporting Compilation Results 1.10. Clearing Compilation Results 1.11. Integrating Other EDA Tools 1.12. Compiler Optimization Techniques 1.13. Compilation Monitoring Mode 1.14. Viewing Quartus Database File Information 1.15. Understanding the Design Netlist Infrastructure 1.16. Using Synopsys* Design Constraint (SDC) on RTL Files 1.17. Using the Node Finder 1.18. Synthesis Language Support 1.19. Synthesis Settings Reference 1.20. Fitter Settings Reference 1.21. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Using the Compilation Dashboard
1.2. Design Analysis & Elaboration x
1.2.1. Locating Design Elements 1.2.2. Using the RTL Analyzer
1.2.1. Locating Design Elements x
1.2.1.1. Copying Hierarchy Path Names
1.2.2. Using the RTL Analyzer x
1.2.2.1. Sweep Hints Viewer 1.2.2.2. Object Set Console 1.2.2.3. Module Interfaces 1.2.2.4. Bundled Instances 1.2.2.5. Auto-hide Unconnected Pins 1.2.2.6. Filtering Ports and Nets 1.2.2.7. Expand Connections
1.3. Design Synthesis x
1.3.1. Preparing for Design Synthesis 1.3.2. Running Synthesis 1.3.3. Post-Synthesis Static Timing Analysis (STA) 1.3.4. Viewing Synthesis Reports
1.3.2. Running Synthesis x
1.3.2.1. Preserving Registers During Synthesis 1.3.2.2. Preserving Signals for Monitoring and Debugging
1.3.4. Viewing Synthesis Reports x
1.3.4.1. Viewing IP Core License Data 1.3.4.2. Viewing Synthesis Dynamic Report Executing Tcl Commands
1.4. Design Place and Route x
1.4.1. Running the Fitter 1.4.2. Viewing Fitter Reports
1.4.1. Running the Fitter x
1.4.1.1. Fitter Commands 1.4.1.2. Disabling or Enabling Physical Synthesis Optimization
1.4.2. Viewing Fitter Reports x
1.4.2.1. Plan Stage Reports 1.4.2.2. Place Stage Reports 1.4.2.3. Route Stage Reports 1.4.2.4. Retime Stage Reports 1.4.2.5. Finalize Stage Reports
1.4.2.2. Place Stage Reports x
1.4.2.2.1. Global Signal Visualization Report
1.4.2.3. Route Stage Reports x
1.4.2.3.1. Global Router Congestion Hotspot Summary Report 1.4.2.3.2. Global Router Wire Utilization Map Report
1.5. Incremental Optimization Flow x
1.5.1. Concurrent Analysis During Synthesis or Fitting 1.5.2. Analyzing Compiler Snapshots 1.5.3. Validating Periphery (I/O) after the Plan Stage
1.5.2. Analyzing Compiler Snapshots x
1.5.2.1. Running Snapshot Viewer
1.5.2.1. Running Snapshot Viewer x
1.5.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.5.2.1.2. Analyzing Clocking with Snapshot Viewer 1.5.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.5.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.5.2.1.5. Analyzing Congestion with Snapshot Viewer
1.6. Fast Forward Compilation Flow x
1.6.1. Step 1: Run Register Retiming 1.6.2. Step 2: Review Retiming Results 1.6.3. Step 3: Run Fast Forward Compile 1.6.4. Step 4: Review Fast Forward Results 1.6.5. Step 5: Implement Fast Forward Recommendations 1.6.6. Retiming Restrictions and Workarounds
1.6.2. Step 2: Review Retiming Results x
1.6.2.1. Locate Critical Chains
1.6.3. Step 3: Run Fast Forward Compile x
1.6.3.1. Fast Forward Compile By Hierarchy 1.6.3.2. HyperFlex Settings
1.6.4. Step 4: Review Fast Forward Results x
1.6.4.1. Clock Fmax Summary Report 1.6.4.2. Fast Forward Details Report
1.7. Full Compilation Flow x
1.7.1. Full Compilation Flow with Temporary Optimization Mode
1.9. Exporting Compilation Results x
1.9.1. Exporting a Version-Compatible Compilation Database 1.9.2. Importing a Version-Compatible Compilation Database 1.9.3. Creating a Design Partition 1.9.4. Exporting a Design Partition 1.9.5. Reusing a Design Partition
1.11. Integrating Other EDA Tools x
1.11.1. Generating a VQM Netlist for other EDA Tools
1.12. Compiler Optimization Techniques x
1.12.1. Compiler Optimization Modes 1.12.2. Allow Register Retiming 1.12.3. Automatic Gated Clock Conversion 1.12.4. Enable Intermediate Fitter Snapshots 1.12.5. Fast Preserve Option 1.12.6. Fractal Synthesis Optimization
1.12.6. Fractal Synthesis Optimization x
1.12.6.1. Enabling or Disabling Fractal Synthesis
1.14. Viewing Quartus Database File Information x
1.14.1. QDB File Attribute Types
1.15. Understanding the Design Netlist Infrastructure x
1.15.1. DNI Netlist Five-Box Data Model
1.15.1. DNI Netlist Five-Box Data Model x
1.15.1.1. Use Case Examples
1.15.1.1. Use Case Examples x
1.15.1.1.1. Scripting Routine Tasks Using Tcl Commands 1.15.1.1.2. Traversing the Design Netlist Using Tcl Commands
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.16.1. Registering the SDC-on-RTL SDC File 1.16.2. Applying the SDC-on-RTL Constraints 1.16.3. Inspecting SDC-on-RTL Constraints 1.16.4. Creating Constraints in SDC-on-RTL SDC Files 1.16.5. Using Entity-Based SDC-on-RTL Constraints 1.16.6. Types of SDC Files Used in the Quartus® Prime Software
1.16.4. Creating Constraints in SDC-on-RTL SDC Files x
1.16.4.1. Example: Using SDC-on-RTL Features
1.16.4.1. Example: Using SDC-on-RTL Features x
1.16.4.1.1. SDC-on RTL Example: Targeting Pins of Top-level Instances 1.16.4.1.2. SDC-on RTL Example: Targeting Pins in Cells 1.16.4.1.3. SDC-on RTL Example: Targeting Pins Using Wildcards 1.16.4.1.4. SDC-on RTL Example: Applying Constraints at Deeper Hierarchies
1.16.5. Using Entity-Based SDC-on-RTL Constraints x
1.16.5.1. Entity-based SDC-on-RTL Constraints Example
1.17. Using the Node Finder x
1.17.1. Node Finder Settings Reference
1.18. Synthesis Language Support x
1.18.1. Verilog and SystemVerilog Synthesis Support 1.18.2. VHDL Synthesis Support
1.18.1. Verilog and SystemVerilog Synthesis Support x
1.18.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.18.1.2. Design Libraries 1.18.1.3. Verilog HDL Configuration 1.18.1.4. Initial Constructs and Memory System Tasks 1.18.1.5. Verilog HDL Macros
1.18.1.3. Verilog HDL Configuration x
1.18.1.3.1. Hierarchical Design Configurations
1.18.2. VHDL Synthesis Support x
1.18.2.1. VHDL Input Settings (Settings Dialog Box) 1.18.2.2. VHDL Standard Libraries and Packages 1.18.2.3. VHDL wait Constructs 1.18.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.19. Synthesis Settings Reference x
1.19.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Compilation on a Compute Farm 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Running the ECO Compilation Flow 2.2.4. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time x
2.3.1. Using Precompiled Component Generation 2.3.2. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.3. Use Appropriate Coding Style to Reduce Synthesis Time
2.3.1. Using Precompiled Component Generation x
2.3.1.1. Enabling Precompiled Components Generation 2.3.1.2. Precompiled Component Generation Flow
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion 2.5.2. Changing Fitter Aggressive Routability Optimization Settings
2.5.1. Identifying Routing Congestion x
2.5.1.1. Identifying Congestion with the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map 2.5.1.2. Identifying Routing Congestion with the Chip Planner
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.3.4.2. Viewing Synthesis Dynamic Report

The dynamic report feature allows you to interact with a full report that displays only a few items in the GUI. This feature is off by default, and you can enable it through the synth_rpt_enable_dynamic_report QSF. Currently, you can view dynamic reports only for the Registers Removed During Synthesis report.

In the following report, you can observe that the compiler removed 12984 registers during synthesis. However, after 2780 registers, the remaining registers are truncated from the report due to the GUI threshold. With the dynamic report feature, you can retrieve details of these remaining registers without recompiling your design using the updated GUI threshold.

Note: You can modify the number of removed registers reported through the Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) > Number of Removed Registers Reported in Synthesis Report option.
Figure 42. Sample Registers Removed During Synthesis Report

Within one compilation, the compiler stores all items from the report in a dynamic SQLite database under <project_directory>/dynamic_report/registers_removed.sqlite. After design synthesis, you can access the SQLite database through Tcl commands to extract a summary of the SQLite database (for example, data column and total size of the items), query from the database using SQL commands (for example, SELECT and WHERE), and retrieve the desired number of truncated lines from the report.

Note:
  • If you recompile after generating the SQLite database, contents are rewritten to the same database. If you turn off the QSF during recompilation, the SQLite database retains the information from the previous compile.
  • If your design does not contain registers to be removed during synthesis, the compiler does not generate the Registers Removed During Synthesis report. Hence, the dynamic_report directory and the SQLite database are also not generated.

Executing Tcl Commands

You can execute the dynamic_report Tcl commands in one of the following ways:

  • Include Tcl commands in a Tcl script and run it using quartus_syn -t <name>.tcl.
  • Execute a single command directly from your terminal as quartus_syn --tcl_eval <tcl command> .
  • Execute a single command from the GUI by launching your project in the Quartus® Prime software and navigating to View > Tcl Console on the menu. In the Tcl Console window, type your Tcl command.

The result is the same irrespective of the method you use to execute your dynamic_report Tcl command.

Note: When you execute a dynamic_report Tcl command, the Tcl command attempts to open the corresponding SQLite database immediately for further action. The path to open the database is absolute. So, you must ensure that your current directory is where your design is located and not in the dynamic_report directory. Otherwise, an error displays indicating the path to the SQLite database is incorrect or an issue with opening the SQLite database.

The following table lists some example dynamic_report Tcl commands with various options:

Table 10.   dynamic_report Tcl Command Examples
dynamic_report Command Option Description Tcl Command Example
-help Provides detailed help for the dynamic_report Tcl command, including currently supported report values, options, and error values. dynamic_report -help
-long_help Provides long help for the dynamic_report Tcl command with examples and possible return values. dynamic_report -long_help
-report <report name> Targets the report that <report name> specifies. For the Registers Removed During Synthesis report, use "registers removed".
Note: The -report option is mandatory as the Tcl command takes further action based on the report name. Absence of the -report option or using an unsupported value for <report name> results in an error.
dynamic_report -report "registers removed"
-summary Generates a summary of the specified report, such as the table name, total size, and column names, which help query from the SQLite database. dynamic_report -report "registers removed" -summary
-query <sqlite query> Accepts an entire SQLite query as an option to retrieve the desired result from the database. For example, -query "SELECT * FROM <table> WHERE <column> = <...>"

If the query command is incorrect or incomplete, an error message displays with details.

The result of this query is sent to an output file under the <project directory>/dynamic_report directory in ASCII format by default.

dynamic_report -report "registers removed" -query "SELECT * FROM 'Registers Removed During Synthesis' WHERE reason = 'Stuck at VCC due to stuck port data_in'"
-dump_all Dumps all items in the report.

The result of this query is sent to an output file under the <project directory>/dynamic_report directory in ASCII format by default.

dynamic_report -report "registers removed" -dump_all
-dump_lines <unsigned integer> Dumps first <unsigned integer> of lines in the report. An error message displays if the value specified for <unsigned integer> is not an unsigned integer or not in the range of 1 and 999999999.

The result of this query is sent to an output file under the <project directory>/dynamic_report directory in ASCII format by default.

dynamic_report -report "registers removed" -dump_lines 250
-filename <file_name> Specifies an output file name for the results dumped by -query, -dump_all, and -dump_lines options.

-filename is optional. If you do not specify a file name, the compiler names the output file as <report name>.ascii. An error message displays if the file name is empty or contains special characters or spaces.

Note: With the -filename option, you can use the -html or -xml option to generate the output file in HTML or XML format, respectively.
dynamic_report -report "registers removed" -dump_all -filename "my_result"
Attention: The options -summary, -query, -dump_all, and -dump_lines are mandatory but exclusive, which means that the dynamic_report Tcl command requires only one option. If you include multiple options within a single dynamic_report Tcl command, an error message displays requesting you to specify a single option.
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