Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Design Analysis & Elaboration 1.3. Design Synthesis 1.4. Design Place and Route 1.5. Incremental Optimization Flow 1.6. Fast Forward Compilation Flow 1.7. Full Compilation Flow 1.8. HSSI Dual Simplex IP Generation Flow 1.9. Exporting Compilation Results 1.10. Clearing Compilation Results 1.11. Integrating Other EDA Tools 1.12. Compiler Optimization Techniques 1.13. Compilation Monitoring Mode 1.14. Viewing Quartus Database File Information 1.15. Understanding the Design Netlist Infrastructure 1.16. Using Synopsys* Design Constraint (SDC) on RTL Files 1.17. Using the Node Finder 1.18. Synthesis Language Support 1.19. Synthesis Settings Reference 1.20. Fitter Settings Reference 1.21. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Using the Compilation Dashboard
1.2. Design Analysis & Elaboration x
1.2.1. Locating Design Elements 1.2.2. Using the RTL Analyzer
1.2.1. Locating Design Elements x
1.2.1.1. Copying Hierarchy Path Names
1.2.2. Using the RTL Analyzer x
1.2.2.1. Sweep Hints Viewer 1.2.2.2. Object Set Console 1.2.2.3. Module Interfaces 1.2.2.4. Bundled Instances 1.2.2.5. Auto-hide Unconnected Pins 1.2.2.6. Filtering Ports and Nets 1.2.2.7. Expand Connections
1.3. Design Synthesis x
1.3.1. Preparing for Design Synthesis 1.3.2. Running Synthesis 1.3.3. Post-Synthesis Static Timing Analysis (STA) 1.3.4. Viewing Synthesis Reports
1.3.2. Running Synthesis x
1.3.2.1. Preserving Registers During Synthesis 1.3.2.2. Preserving Signals for Monitoring and Debugging
1.3.4. Viewing Synthesis Reports x
1.3.4.1. Viewing IP Core License Data 1.3.4.2. Viewing Synthesis Dynamic Report
1.4. Design Place and Route x
1.4.1. Running the Fitter 1.4.2. Viewing Fitter Reports
1.4.1. Running the Fitter x
1.4.1.1. Fitter Commands 1.4.1.2. Disabling or Enabling Physical Synthesis Optimization
1.4.2. Viewing Fitter Reports x
1.4.2.1. Plan Stage Reports 1.4.2.2. Place Stage Reports 1.4.2.3. Route Stage Reports 1.4.2.4. Retime Stage Reports 1.4.2.5. Finalize Stage Reports
1.4.2.2. Place Stage Reports x
1.4.2.2.1. Global Signal Visualization Report
1.4.2.3. Route Stage Reports x
1.4.2.3.1. Global Router Congestion Hotspot Summary Report 1.4.2.3.2. Global Router Wire Utilization Map Report
1.5. Incremental Optimization Flow x
1.5.1. Concurrent Analysis During Synthesis or Fitting 1.5.2. Analyzing Compiler Snapshots 1.5.3. Validating Periphery (I/O) after the Plan Stage
1.5.2. Analyzing Compiler Snapshots x
1.5.2.1. Running Snapshot Viewer
1.5.2.1. Running Snapshot Viewer x
1.5.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.5.2.1.2. Analyzing Clocking with Snapshot Viewer 1.5.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.5.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.5.2.1.5. Analyzing Congestion with Snapshot Viewer
1.6. Fast Forward Compilation Flow x
1.6.1. Step 1: Run Register Retiming 1.6.2. Step 2: Review Retiming Results 1.6.3. Step 3: Run Fast Forward Compile 1.6.4. Step 4: Review Fast Forward Results 1.6.5. Step 5: Implement Fast Forward Recommendations 1.6.6. Retiming Restrictions and Workarounds
1.6.2. Step 2: Review Retiming Results x
1.6.2.1. Locate Critical Chains
1.6.3. Step 3: Run Fast Forward Compile x
1.6.3.1. Fast Forward Compile By Hierarchy 1.6.3.2. HyperFlex Settings
1.6.4. Step 4: Review Fast Forward Results x
1.6.4.1. Clock Fmax Summary Report 1.6.4.2. Fast Forward Details Report
1.7. Full Compilation Flow x
1.7.1. Full Compilation Flow with Temporary Optimization Mode
1.9. Exporting Compilation Results x
1.9.1. Exporting a Version-Compatible Compilation Database 1.9.2. Importing a Version-Compatible Compilation Database 1.9.3. Creating a Design Partition 1.9.4. Exporting a Design Partition 1.9.5. Reusing a Design Partition
1.11. Integrating Other EDA Tools x
1.11.1. Generating a VQM Netlist for other EDA Tools
1.12. Compiler Optimization Techniques x
1.12.1. Compiler Optimization Modes 1.12.2. Allow Register Retiming 1.12.3. Automatic Gated Clock Conversion 1.12.4. Enable Intermediate Fitter Snapshots 1.12.5. Fast Preserve Option 1.12.6. Fractal Synthesis Optimization
1.12.6. Fractal Synthesis Optimization x
1.12.6.1. Enabling or Disabling Fractal Synthesis
1.14. Viewing Quartus Database File Information x
1.14.1. QDB File Attribute Types
1.15. Understanding the Design Netlist Infrastructure x
1.15.1. DNI Netlist Five-Box Data Model
1.15.1. DNI Netlist Five-Box Data Model x
1.15.1.1. Use Case Examples
1.15.1.1. Use Case Examples x
1.15.1.1.1. Scripting Routine Tasks Using Tcl Commands 1.15.1.1.2. Traversing the Design Netlist Using Tcl Commands
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.16.1. Registering the SDC-on-RTL SDC File 1.16.2. Applying the SDC-on-RTL Constraints 1.16.3. Inspecting SDC-on-RTL Constraints Tcl Console RTL Analyzer Quartus® Prime Timing Analyzer 1.16.4. Creating Constraints in SDC-on-RTL SDC Files 1.16.5. Using Entity-Based SDC-on-RTL Constraints 1.16.6. Types of SDC Files Used in the Quartus® Prime Software
1.16.4. Creating Constraints in SDC-on-RTL SDC Files x
1.16.4.1. Example: Using SDC-on-RTL Features
1.16.4.1. Example: Using SDC-on-RTL Features x
1.16.4.1.1. SDC-on RTL Example: Targeting Pins of Top-level Instances 1.16.4.1.2. SDC-on RTL Example: Targeting Pins in Cells 1.16.4.1.3. SDC-on RTL Example: Targeting Pins Using Wildcards 1.16.4.1.4. SDC-on RTL Example: Applying Constraints at Deeper Hierarchies
1.16.5. Using Entity-Based SDC-on-RTL Constraints x
1.16.5.1. Entity-based SDC-on-RTL Constraints Example
1.17. Using the Node Finder x
1.17.1. Node Finder Settings Reference
1.18. Synthesis Language Support x
1.18.1. Verilog and SystemVerilog Synthesis Support 1.18.2. VHDL Synthesis Support
1.18.1. Verilog and SystemVerilog Synthesis Support x
1.18.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.18.1.2. Design Libraries 1.18.1.3. Verilog HDL Configuration 1.18.1.4. Initial Constructs and Memory System Tasks 1.18.1.5. Verilog HDL Macros
1.18.1.3. Verilog HDL Configuration x
1.18.1.3.1. Hierarchical Design Configurations
1.18.2. VHDL Synthesis Support x
1.18.2.1. VHDL Input Settings (Settings Dialog Box) 1.18.2.2. VHDL Standard Libraries and Packages 1.18.2.3. VHDL wait Constructs 1.18.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.19. Synthesis Settings Reference x
1.19.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Compilation on a Compute Farm 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Running the ECO Compilation Flow 2.2.4. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time x
2.3.1. Using Precompiled Component Generation 2.3.2. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.3. Use Appropriate Coding Style to Reduce Synthesis Time
2.3.1. Using Precompiled Component Generation x
2.3.1.1. Enabling Precompiled Components Generation 2.3.1.2. Precompiled Component Generation Flow
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion 2.5.2. Changing Fitter Aggressive Routability Optimization Settings
2.5.1. Identifying Routing Congestion x
2.5.1.1. Identifying Congestion with the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map 2.5.1.2. Identifying Routing Congestion with the Chip Planner
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.16.3. Inspecting SDC-on-RTL Constraints

You can access SDC-on-RTL constraints in multiple ways in the order of the earliest opportunity in the flow, as described in the following sections:
Note: In all of the methods discussed in this section, the SDC-on-RTL constraints are read-only. You cannot modify the constraints in the compilation flow. You can only change the constraints by changing the source RTL SDC file and reloading it during Analysis and Elaboration.

Tcl Console

The Tcl console allows you to experiment conveniently with targeting constraints and the related syntax. The netlist is read-only when accessed from the Tcl console, and constraint commands are not saved into the design database.

Access the Tcl Console through the command-line interface using the following command: 
quartus_syn -s

Once the Analysis & Elaboration compilation stage completes, you can load the project in the console (project_open <project_name>) and load the appropriate checkpoint using the dni::load_design -checkpoint "constrained" command. You can now perform tasks such as:

  • Read a specific SDC file using the dni::read_sdc<file_name> command.
  • Dump constraints using the dni::write_sdc command.
  • Run constraint commands that are limited to the local session. For more information, refer to Creating Constraints in SDC-on-RTL SDC Files.

RTL Analyzer

To invoke the RTL Analyzer (Constrained mode) from the compilation dashboard, enable the RTL Analysis Debug Mode option under Project > Settings as described in Analysis & Elaboration. The RTL Analyzer GUI allows you to view the constraints on the design netlist. When you select a netlist object in the schematic viewer or Netlist Navigator, you can view constraints targeting that object in the Property viewer. This helps ensure the constraints target the intended nodes in your RTL.

In the following example, when you select iopll_refclk[1:0] and right-click and select Display Individual Bits from its context-sensitive menu, the Connectivity Details pop-up window displays its ports. When you select one of the ports, constraints applied to the port are displayed in a separate Constraints tab, as shown in the following image:

Figure 119. Viewing Constraints in the RTL Analyzer

Besides the constraints of the selected object, the Constraints tab also includes constraints of the associated object. For example, a net bus’ constraints are included along with the net's constraints, an instance bus’ constraints with the instance’s constraint, and so on.

Figure 120. Viewing Constraints of Associated Objects
Note: You can cross-probe the SDC file by right-clicking on a constraint in the Property viewer and selecting the View in Source option.

You can also launch the Constraints dialog box (Tools > Object Constraints) from the RTL Analyzer menu to view a list of all constraints (assignments and timing-related SDC). It allows you to select an assignment or a constraint and cross-probe to its source file by right-clicking and selecting View in Source. The source file that contains the assignment or constraint launches in the Quartus® Prime GUI with the assignment line highlighted.

Figure 121. Object Constraints

The Constraints GUI allows you to filter four types of constraints:

  • Global Assignments: Assignments that are created with the set_global_assignment command.
  • Source Assignments: Assignments embedded in source RTLs.
  • Instance Assignments: Assignments created with the set_instance_assignment command.
  • Timing Constraints (SDC): Constraints created through SDC-on-RTL. They usually appear in the Constrained view of the Analysis & Synthesis stage. If no SDC is read in, the Timing Constraints (SDC) option is disabled. This can happen in views before SDC are read in, for example, in "Elaborated" and "Instrumented" views of the Analysis & Synthesis stage or when no SDC-on-RTL file is read in.

You can filter the constraints further using the filtering field to view constraints matching the string. It supports filtering through command name, file name, and line number. You can also sort the constraints using the Command, File, and Line column header.

Figure 122. Filtering Constraints

Through the context-sensitive menu of the Constraints GUI, you can view the selected constraints in its source file or the objects that it applies to.

Figure 123. Context-Sensitive Menu of the Constraints GUI

You can view objects that a constraint apply to through the Show Constrained Objects option, which displays the Constrained Objects dialog. In the Constrained Objects, you can select the constrained object through its context-sensitive menu. This allows you to view the object's property in the Property Viewer. You can also apply a color to each constrained object by clicking Create Color Set.

Figure 124. Constrained Objects

Quartus® Prime Timing Analyzer

The Quartus® Prime Timing Analyzer uses industry-standard constraint and analysis methodology to report on all data required times, data arrival times, and clock arrival times for all register-to-register, I/O, and asynchronous reset paths in your design. The Timing Analyzer verifies that the required timing relationships are met for your design to function correctly and confirms actual signal arrival times against the constraints you specify. For more information about the Timing Analyzer, refer to the Quartus® Prime Pro Edition User Guide: Timing Analyzer .

Using the Timing Analyzer GUI or Tcl command console, you can load SDC-on-RTL constraints into the timing analysis session by running the read_sdc command. By default, the read_sdc command always loads SDC-on-RTL constraints, which happens before loading other conventional Quartus® Prime software SDC files (SDC_FILE ).

During static timing analysis, you can load only the SDC-on-RTL SDC constraints using the import_sdc command. This is helpful when debugging issues you suspect are caused by SDC-on-RTL constraints.

To disable the loading of SDC-on-RTL constraints during the calls to read_sdc, use the read_sdc -no_import option or set the QSF variable ENABLE_IMPORT_SDC_DURING_READ_SDC to OFF.

Note: If you change the actual SDC-on-RTL files and import them using read_sdc or import_sdc command without rerunning Analysis & Elaboration, the Timing Analyzer issues a warning message informing you that changes to the SDC-on-RTL files will not be observed until Analysis & Elaboration is rerun.

Once you import the constraints using the read_sdc or import_sdc command, they become standard constraints in the Timing Analyzer. Standard constraint diagnostic reports (report_exceptions, report_sdc, and so on) operate on these constraints, and you can update the constraints for the current Timing Analyzer session using the existing Quartus® Prime timing analysis API commands.

Note: You can cross-probe the constraints in the report_sdc by right-clicking on the Location column of a constraint and selecting Locate in Constraint File.
Figure 125. SDC Report in the Timing Analyzer
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