Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Design Analysis & Elaboration 1.3. Design Synthesis 1.4. Design Place and Route 1.5. Incremental Optimization Flow 1.6. Fast Forward Compilation Flow 1.7. Full Compilation Flow 1.8. HSSI Dual Simplex IP Generation Flow 1.9. Exporting Compilation Results 1.10. Clearing Compilation Results 1.11. Integrating Other EDA Tools 1.12. Compiler Optimization Techniques 1.13. Compilation Monitoring Mode 1.14. Viewing Quartus Database File Information 1.15. Understanding the Design Netlist Infrastructure 1.16. Using Synopsys* Design Constraint (SDC) on RTL Files 1.17. Using the Node Finder 1.18. Synthesis Language Support 1.19. Synthesis Settings Reference 1.20. Fitter Settings Reference 1.21. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Using the Compilation Dashboard
1.2. Design Analysis & Elaboration x
1.2.1. Locating Design Elements 1.2.2. Using the RTL Analyzer
1.2.1. Locating Design Elements x
1.2.1.1. Copying Hierarchy Path Names
1.2.2. Using the RTL Analyzer x
1.2.2.1. Sweep Hints Viewer 1.2.2.2. Object Set Console 1.2.2.3. Module Interfaces 1.2.2.4. Bundled Instances 1.2.2.5. Auto-hide Unconnected Pins 1.2.2.6. Filtering Ports and Nets 1.2.2.7. Expand Connections
1.3. Design Synthesis x
1.3.1. Preparing for Design Synthesis 1.3.2. Running Synthesis 1.3.3. Post-Synthesis Static Timing Analysis (STA) 1.3.4. Viewing Synthesis Reports
1.3.2. Running Synthesis x
1.3.2.1. Preserving Registers During Synthesis 1.3.2.2. Preserving Signals for Monitoring and Debugging
1.3.4. Viewing Synthesis Reports x
1.3.4.1. Viewing IP Core License Data 1.3.4.2. Viewing Synthesis Dynamic Report
1.4. Design Place and Route x
1.4.1. Running the Fitter 1.4.2. Viewing Fitter Reports
1.4.1. Running the Fitter x
1.4.1.1. Fitter Commands 1.4.1.2. Disabling or Enabling Physical Synthesis Optimization
1.4.2. Viewing Fitter Reports x
1.4.2.1. Plan Stage Reports 1.4.2.2. Place Stage Reports 1.4.2.3. Route Stage Reports 1.4.2.4. Retime Stage Reports 1.4.2.5. Finalize Stage Reports
1.4.2.2. Place Stage Reports x
1.4.2.2.1. Global Signal Visualization Report
1.4.2.3. Route Stage Reports x
1.4.2.3.1. Global Router Congestion Hotspot Summary Report 1.4.2.3.2. Global Router Wire Utilization Map Report
1.5. Incremental Optimization Flow x
1.5.1. Concurrent Analysis During Synthesis or Fitting 1.5.2. Analyzing Compiler Snapshots 1.5.3. Validating Periphery (I/O) after the Plan Stage
1.5.2. Analyzing Compiler Snapshots x
1.5.2.1. Running Snapshot Viewer
1.5.2.1. Running Snapshot Viewer x
1.5.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.5.2.1.2. Analyzing Clocking with Snapshot Viewer 1.5.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.5.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.5.2.1.5. Analyzing Congestion with Snapshot Viewer
1.6. Fast Forward Compilation Flow x
1.6.1. Step 1: Run Register Retiming 1.6.2. Step 2: Review Retiming Results 1.6.3. Step 3: Run Fast Forward Compile 1.6.4. Step 4: Review Fast Forward Results 1.6.5. Step 5: Implement Fast Forward Recommendations 1.6.6. Retiming Restrictions and Workarounds
1.6.2. Step 2: Review Retiming Results x
1.6.2.1. Locate Critical Chains
1.6.3. Step 3: Run Fast Forward Compile x
1.6.3.1. Fast Forward Compile By Hierarchy 1.6.3.2. HyperFlex Settings
1.6.4. Step 4: Review Fast Forward Results x
1.6.4.1. Clock Fmax Summary Report 1.6.4.2. Fast Forward Details Report
1.7. Full Compilation Flow x
1.7.1. Full Compilation Flow with Temporary Optimization Mode
1.9. Exporting Compilation Results x
1.9.1. Exporting a Version-Compatible Compilation Database 1.9.2. Importing a Version-Compatible Compilation Database 1.9.3. Creating a Design Partition 1.9.4. Exporting a Design Partition 1.9.5. Reusing a Design Partition
1.11. Integrating Other EDA Tools x
1.11.1. Generating a VQM Netlist for other EDA Tools
1.12. Compiler Optimization Techniques x
1.12.1. Compiler Optimization Modes 1.12.2. Allow Register Retiming 1.12.3. Automatic Gated Clock Conversion 1.12.4. Enable Intermediate Fitter Snapshots 1.12.5. Fast Preserve Option 1.12.6. Fractal Synthesis Optimization
1.12.6. Fractal Synthesis Optimization x
1.12.6.1. Enabling or Disabling Fractal Synthesis
1.14. Viewing Quartus Database File Information x
1.14.1. QDB File Attribute Types
1.15. Understanding the Design Netlist Infrastructure x
1.15.1. DNI Netlist Five-Box Data Model
1.15.1. DNI Netlist Five-Box Data Model x
1.15.1.1. Use Case Examples
1.15.1.1. Use Case Examples x
1.15.1.1.1. Scripting Routine Tasks Using Tcl Commands 1.15.1.1.2. Traversing the Design Netlist Using Tcl Commands Traversing Basic Design Objects Getting Selective Design Objects
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.16.1. Registering the SDC-on-RTL SDC File 1.16.2. Applying the SDC-on-RTL Constraints 1.16.3. Inspecting SDC-on-RTL Constraints 1.16.4. Creating Constraints in SDC-on-RTL SDC Files 1.16.5. Using Entity-Based SDC-on-RTL Constraints 1.16.6. Types of SDC Files Used in the Quartus® Prime Software
1.16.4. Creating Constraints in SDC-on-RTL SDC Files x
1.16.4.1. Example: Using SDC-on-RTL Features
1.16.4.1. Example: Using SDC-on-RTL Features x
1.16.4.1.1. SDC-on RTL Example: Targeting Pins of Top-level Instances 1.16.4.1.2. SDC-on RTL Example: Targeting Pins in Cells 1.16.4.1.3. SDC-on RTL Example: Targeting Pins Using Wildcards 1.16.4.1.4. SDC-on RTL Example: Applying Constraints at Deeper Hierarchies
1.16.5. Using Entity-Based SDC-on-RTL Constraints x
1.16.5.1. Entity-based SDC-on-RTL Constraints Example
1.17. Using the Node Finder x
1.17.1. Node Finder Settings Reference
1.18. Synthesis Language Support x
1.18.1. Verilog and SystemVerilog Synthesis Support 1.18.2. VHDL Synthesis Support
1.18.1. Verilog and SystemVerilog Synthesis Support x
1.18.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.18.1.2. Design Libraries 1.18.1.3. Verilog HDL Configuration 1.18.1.4. Initial Constructs and Memory System Tasks 1.18.1.5. Verilog HDL Macros
1.18.1.3. Verilog HDL Configuration x
1.18.1.3.1. Hierarchical Design Configurations
1.18.2. VHDL Synthesis Support x
1.18.2.1. VHDL Input Settings (Settings Dialog Box) 1.18.2.2. VHDL Standard Libraries and Packages 1.18.2.3. VHDL wait Constructs 1.18.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.19. Synthesis Settings Reference x
1.19.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Compilation on a Compute Farm 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Running the ECO Compilation Flow 2.2.4. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time x
2.3.1. Using Precompiled Component Generation 2.3.2. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.3. Use Appropriate Coding Style to Reduce Synthesis Time
2.3.1. Using Precompiled Component Generation x
2.3.1.1. Enabling Precompiled Components Generation 2.3.1.2. Precompiled Component Generation Flow
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion 2.5.2. Changing Fitter Aggressive Routability Optimization Settings
2.5.1. Identifying Routing Congestion x
2.5.1.1. Identifying Congestion with the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map 2.5.1.2. Identifying Routing Congestion with the Chip Planner
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.15.1.1.2. Traversing the Design Netlist Using Tcl Commands

In this topic, you can see examples of Tcl commands that you can use to extract basic netlist objects or selective objects of your design using filters, pattern, and other techniques.

Traversing Basic Design Objects

The following table lists Tcl command examples for extracting hierarchical instances, instance ports, nets, and ports from your design netlist:

Note: When using dni:: Tcl commands in an SDC file, you can skip adding dni:: as read_sdc adds the namespace correctly.
Table 27.  Tcl Commands for Traversing Design Objects
Task Tcl Command Example
Get all instances directly under the top module. foreach_in_collection obj [dni::get_cells] { puts $obj; }
Get all design instances at all hierarchies. foreach_in_collection obj [dni::get_cells -hierarchical] { puts $obj; }
Get all instances directly under a hierarchical instance using a pattern with the hierarchy separator (|). foreach_in_collection obj [dni::get_cells auto|*] { puts $obj; }
Get all direct child instances of a specific hierarchical instance (for example, the instance auto).

# Use dni::current_instance to move the browsing scope to the auto hierarchical instance.

dni::current_instance auto

# Get all direct child instances of the hierarchical instance auto.

foreach_in_collection obj [dni::get_cells] { puts $obj; }

# Set the scope back to top design

dni::current_instance

Get all nets directly under the top module. foreach_in_collection obj [dni::get_nets] { puts $obj; }
Get all nets of the design at all hierarchies. foreach_in_collection obj [dni::get_nets -hierarchical] { puts $obj; }
Get all nets directly under a hierarchical instance using a pattern with the hierarchy separator (|). foreach_in_collection obj [dni::get_nets tick|*] { puts $obj; }
Get all nets directly under a specific hierarchical instance (for example, the instance tick).

# Use dni::current_instance to move the browsing scope to the tickhierarchical instance.

dni::current_instance tick

# Get all nets directly under tick

foreach_in_collection obj [dni::get_nets] { puts $obj; }

# Set the scope back to top design

dni::current_instance

Get all ports of the design. foreach_in_collection obj [dni::get_ports] { puts $obj; }
Get all instance ports of direct child instances under the design top module. foreach_in_collection obj [dni::get_pins] { puts $obj; }
Get all instance ports of all child instances under a specific hierarchical instance (for example, tick).

# Use dni::current_instance to move the browsing scope to the tick hierarchical instance.

dni::current_instance tick

# Get all instance ports under tick

foreach_in_collection obj [dni::get_pins] { puts $obj; }

# Set the scope back to the top design

dni::current_instance

Get all instance ports on all child instances using the object ID format to specify a hierarchical instance.

set inst [get_cells tick]

foreach_in_collection obj [dni::get_pins -of_objects $inst] { puts $obj; }

foreach_in_collection obj [dni::get_pins -of_objects tick|ticket[1]] { puts $obj; }

foreach_in_collection obj [dni::get_pins -of_objects instance::chiptrip::tick|ticket[1]] { puts $obj; }

Getting Selective Design Objects

You can use the following techniques to refine your search criteria and extract select design objects from your netlist:

  • <patterns> : It extracts objects by matching patterns in dni::get_cells, dni::get_nets, and dni::get_pins commands. Patterns can include wildcard characters * or ?. Wildcard characters do not match with the hierarchical separator.

    For objects in the design hierarchy:

    • The hierarchical path name of the object is matched against the pattern.
    • The hierarchical separator | splits the pattern into individual subpatterns, each of which is matched against one level of hierarchy. This means that a * does not match the hierarchy.
    • The name being matched is relative to the current search root (design top module). You can change the current search root using the dni::current_instance command.
Table 28.  Getting Selective Design Objects Using <pattern>
Tasks Using <pattern> Tcl Command Example
Get all first-level hierarchical and leaf instances. foreach_in_collection obj [dni::get_cells *] { puts $obj; }
Get all second-level hierarchical and leaf instances. foreach_in_collection obj [dni::get_cells *|*] { puts $obj; }
Get all instances under the hierarchical instance, for example, auto. foreach_in_collection obj [dni::get_cells auto|*] { puts $obj; }
Get all nets under the top module. foreach_in_collection obj [dni::get_nets *] { puts $obj; }
Get all nets under the first level hierarchical and leaf instances. foreach_in_collection obj [dni::get_nets *|*] { puts $obj; }
Get all nets under the first-level hierarchical instance, for example, auto. foreach_in_collection obj [dni::get_nets auto|*] { puts $obj; }
Get all instance ports on first-level hierarchical and leaf instances. foreach_in_collection obj [dni::get_pins *|*] { puts $obj; }
Get all instance ports on the hierarchical instance, for example, auto. foreach_in_collection obj [dni::get_pins auto|*] { puts $obj; }
Get all instance ports on all the child instances of the hierarchical instance, for example, auto. foreach_in_collection obj [dni::get_pins auto|*|*] { puts $obj; }
  • <-of_objects> : It extracts related design objects of the input object collection for dni::get_cells, dni::get_nets, dni::get_pins, and dni::get_ports. The following object relationships are considered:
    • dni::get_cells -of_objects <inst_port|net>
    • dni::get_nets -of_objects <inst_port|port|instance>
    • dni::get_pins -of_objects <instance|net>
    • dni::get_ports -of_objects <net>
Table 29.  Getting Selective Design Objects Using <-of_objects>
Tasks Using <-of_objects> Tcl Command Example

Get the hierarchical or leaf instance on which the input instance port is.

foreach_in_collection obj [dni::get_cells -of_objects inst_port::chiptrip::auto|dir[0]] { puts $obj; }

foreach_in_collection obj [dni::get_cells -of_objects inst_port::chiptrip::auto|street_map[2]|q] { puts $obj; }

Get the hierarchical or leaf instances to which the input net is connected.

foreach_in_collection obj [dni::get_cells -of_objects net::chiptrip::wire_get_ticket1] { puts $obj; }

foreach_in_collection obj [dni::get_cells -of_objects net::chiptrip::auto|n5] { puts $obj; }

foreach_in_collection obj [dni::get_cells -of_objects [dni::get_nets *]] { puts $obj; }

foreach_in_collection obj [dni::get_cells -of_objects [dni::get_nets auto|*]] { puts $obj; }

Get the net connecting a leaf instance port. foreach_in_collection obj [dni::get_nets -of_objects inst_port::chiptrip::auto|street_map[0]|q] { puts $obj; }
Get the net connecting a hierarchical instance port. foreach_in_collection obj [dni::get_nets -of_objects inst_port::chiptrip::auto|get_ticket] { puts $obj; }
Get the nets connecting to all the instance ports of a leaf instance. foreach_in_collection obj [dni::get_nets -of_objects instance::chiptrip::auto|street_map[0]] { puts $obj; }
Get the nets connecting to all the instance ports of a hierarchical instance. foreach_in_collection obj [dni::get_nets -of_objects instance::chiptrip::auto] { puts $obj; }
Get the net connecting to a primary port of the design. foreach_in_collection obj [dni::get_nets -of_objects port::chiptrip::gt1] { puts $obj; }
Get instance ports on a leaf instance. foreach_in_collection obj [dni::get_pins -of_objects instance::chiptrip::tick|add_0] { puts $obj; }
Get instance ports on a hierarchical instance. foreach_in_collection obj [dni::get_pins -of_objects instance::chiptrip::tick] { puts $obj; }
Get the instance ports on the hierarchical instance, for example, instance::chiptrip::auto. foreach_in_collection obj [dni::get_pins -of_objects [dni::get_cells auto]] { puts $obj; }
Get instance ports connected by a hierarchical net. foreach_in_collection obj [dni::get_pins -of_objects net::chiptrip::wire_get_ticket1] { puts $obj; }
Get primary ports connected by a hierarchical net on the top level. foreach_in_collection obj [dni::get_ports -of_objects net::chiptrip::wire_get_ticket1] { puts $obj; }
  • <-filter> : It extracts objects by filtering objects returned from dni::get_cells, dni::get_nets, dni::get_pins, and dni::get_ports based on the filter expression. The filter expression verifies every object that satisfies the other search criteria. If the object does not satisfy the filter, it is not returned in the result.
    A filter expression comprises predicates combined using logical operators, such as &&, and/AND, ||, or/OR, and !. Parentheses () in the expression override precedence. Each predicate has the following form: 
    prop_name relop value
    where,
    • prop_name is the name of the object property being evaluated.
    • value is a number or a string. You can provide simple strings without the surrounding double-quotes.
    • relop is one of the following comparison operators:
      • == (equal)
      • != (not equal)
      • =~ (matches, value is then a pattern)
      • !~ (does not match, value is then a pattern)
      • > (greater than)
      • < (less than)
      • >= (greater than or equal to)
      • <= (less than or equal to)

    For example: -filter {name=~"out[*]" && ! (master_name==mod_1 || parent_name != block_1)}

Table 30.  Getting Selective Design Objects Using <-filter>
Tasks Using <-filter> Tcl Command Example
Get all child instances under the top-level. foreach_in_collection obj [dni::get_cells *] { puts $obj; }
Get properties of the instance object type. dni::list_properties -type instance
Get objects that are not a leaf instance foreach_in_collection obj [dni::get_cells * -filter {is_leaf==1}] { puts $obj; }
Get all objects that are hierarchical instances. foreach_in_collection obj [dni::get_cells * -filter {is_leaf==0}] { puts $obj; }
Return hierarchical instances matching the name pattern (for example, t*) under the design top-level module. foreach_in_collection obj [dni::get_cells * -filter {is_leaf==0 && name=~"t*"}] { puts $obj; }
Get all instances under the hierarchical instance, for example, auto that matches the module name in the filter.

foreach_in_collection obj [dni::get_cells auto|*] { puts $obj; }

dni::get_property -name module_name -object instance::chiptrip::auto|Mux_0

foreach_in_collection obj [dni::get_cells auto|* -filter {module_name=="primitive_lib_WORKING_LIBRARY_INTERNAL/OPER_(MUX)"}] { puts $obj; }

Get properties that you can use to filter net objects. Then, get nets with three connected instance ports and primary ports under the top-level design.

dni::list_properties -type net

foreach_in_collection obj [dni::get_nets -filter {number_of_ports==3}] { puts $obj; }

Get all nets in the full design hierarchies that are under the parent module, for example, auto_max. foreach_in_collection obj [dni::get_nets -hierarchical -filter {parent_name=="auto_max"}] { puts $obj; }
Get all nets in the full design hierarchies that are associated with the net_bus, for example, street_map. foreach_in_collection obj [dni::get_nets -hierarchical -filter {net_bus_name=="street_map"} ] { puts $obj; }
Get properties that you can use to filter instance port objects and get the value of the direction property. Then, get all output inst_ports under the top-level design.

dni::list_properties -type inst_port

dni::get_property -name direction -object inst_port::chiptrip::auto|get_ticket

foreach_in_collection obj [dni::get_pins -filter {direction==output}] { puts $obj; }

Get all primary input ports in the design. foreach_in_collection obj [dni::get_ports -filter {direction==input}] { puts $obj; }
  • Combined use of <pattern>, -of_objects <obj_col>, -hierarchical, and -filter <filter_expr> :
Table 31.  Combined Search Criteria
Tasks Using Combined Search Criteria  
Get all instance ports under the design top-module that match the combined search criteria of -of_objects and -filter. foreach_in_collection obj [dni::get_pins -of_objects [dni::get_cells *] -filter {direction==input}] { puts $obj; }
Get all nets under the design top module that match the pattern and -hierarchical. foreach_in_collection obj [dni::get_nets time* -hierarchical] { puts $obj; }
The following example shows the limitation of the combined search criteria: 
tcl> foreach_in_collection obj [dni::get_pins clk -hierarchical]  { puts $obj; }
inst_port::chiptrip::auto|clk
inst_port::chiptrip::speed|clk
inst_port::chiptrip::tick|clk
inst_port::chiptrip::time_c|clk

 
tcl> foreach_in_collection obj [dni::get_nets time* -of_objects instance::chiptrip::time_c] { puts $obj; }
Arguments '-of_objects' and 'patterns' are mutually exclusive

 
tcl> foreach_in_collection obj [dni::get_pins -hierarchical -of_objects instance::chiptrip::time_c]  { puts $obj; }

Arguments '-of_objects' and '-hierarchical' are mutually exclusive
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