Quartus® Prime Pro Edition User Guide: Design Compilation

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ID 683236
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Compilation 2. Reducing Compilation Time 3. Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Design Analysis & Elaboration 1.3. Design Synthesis 1.4. Design Place and Route 1.5. Incremental Optimization Flow 1.6. Fast Forward Compilation Flow 1.7. Full Compilation Flow 1.8. HSSI Dual Simplex IP Generation Flow 1.9. Exporting Compilation Results 1.10. Clearing Compilation Results 1.11. Integrating Other EDA Tools 1.12. Compiler Optimization Techniques 1.13. Compilation Monitoring Mode 1.14. Viewing Quartus Database File Information 1.15. Understanding the Design Netlist Infrastructure 1.16. Using Synopsys* Design Constraint (SDC) on RTL Files 1.17. Using the Node Finder 1.18. Synthesis Language Support 1.19. Synthesis Settings Reference 1.20. Fitter Settings Reference 1.21. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy 1.1.3. Using the Compilation Dashboard
1.2. Design Analysis & Elaboration x
1.2.1. Locating Design Elements 1.2.2. Using the RTL Analyzer
1.2.1. Locating Design Elements x
1.2.1.1. Copying Hierarchy Path Names
1.2.2. Using the RTL Analyzer x
1.2.2.1. Sweep Hints Viewer 1.2.2.2. Object Set Console 1.2.2.3. Module Interfaces 1.2.2.4. Bundled Instances 1.2.2.5. Auto-hide Unconnected Pins 1.2.2.6. Filtering Ports and Nets 1.2.2.7. Expand Connections
1.3. Design Synthesis x
1.3.1. Preparing for Design Synthesis 1.3.2. Running Synthesis 1.3.3. Post-Synthesis Static Timing Analysis (STA) 1.3.4. Viewing Synthesis Reports
1.3.2. Running Synthesis x
1.3.2.1. Preserving Registers During Synthesis 1.3.2.2. Preserving Signals for Monitoring and Debugging
1.3.4. Viewing Synthesis Reports x
1.3.4.1. Viewing IP Core License Data 1.3.4.2. Viewing Synthesis Dynamic Report
1.4. Design Place and Route x
1.4.1. Running the Fitter 1.4.2. Viewing Fitter Reports
1.4.1. Running the Fitter x
1.4.1.1. Fitter Commands 1.4.1.2. Disabling or Enabling Physical Synthesis Optimization
1.4.2. Viewing Fitter Reports x
1.4.2.1. Plan Stage Reports 1.4.2.2. Place Stage Reports 1.4.2.3. Route Stage Reports 1.4.2.4. Retime Stage Reports 1.4.2.5. Finalize Stage Reports
1.4.2.2. Place Stage Reports x
1.4.2.2.1. Global Signal Visualization Report
1.4.2.3. Route Stage Reports x
1.4.2.3.1. Global Router Congestion Hotspot Summary Report 1.4.2.3.2. Global Router Wire Utilization Map Report
1.5. Incremental Optimization Flow x
1.5.1. Concurrent Analysis During Synthesis or Fitting 1.5.2. Analyzing Compiler Snapshots 1.5.3. Validating Periphery (I/O) after the Plan Stage
1.5.2. Analyzing Compiler Snapshots x
1.5.2.1. Running Snapshot Viewer
1.5.2.1. Running Snapshot Viewer x
1.5.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.5.2.1.2. Analyzing Clocking with Snapshot Viewer 1.5.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.5.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.5.2.1.5. Analyzing Congestion with Snapshot Viewer
1.6. Fast Forward Compilation Flow x
1.6.1. Step 1: Run Register Retiming 1.6.2. Step 2: Review Retiming Results 1.6.3. Step 3: Run Fast Forward Compile 1.6.4. Step 4: Review Fast Forward Results 1.6.5. Step 5: Implement Fast Forward Recommendations 1.6.6. Retiming Restrictions and Workarounds
1.6.2. Step 2: Review Retiming Results x
1.6.2.1. Locate Critical Chains
1.6.3. Step 3: Run Fast Forward Compile x
1.6.3.1. Fast Forward Compile By Hierarchy 1.6.3.2. HyperFlex Settings
1.6.4. Step 4: Review Fast Forward Results x
1.6.4.1. Clock Fmax Summary Report 1.6.4.2. Fast Forward Details Report
1.7. Full Compilation Flow x
1.7.1. Full Compilation Flow with Temporary Optimization Mode
1.9. Exporting Compilation Results x
1.9.1. Exporting a Version-Compatible Compilation Database 1.9.2. Importing a Version-Compatible Compilation Database 1.9.3. Creating a Design Partition 1.9.4. Exporting a Design Partition 1.9.5. Reusing a Design Partition
1.11. Integrating Other EDA Tools x
1.11.1. Generating a VQM Netlist for other EDA Tools
1.12. Compiler Optimization Techniques x
1.12.1. Compiler Optimization Modes 1.12.2. Allow Register Retiming 1.12.3. Automatic Gated Clock Conversion 1.12.4. Enable Intermediate Fitter Snapshots 1.12.5. Fast Preserve Option 1.12.6. Fractal Synthesis Optimization
1.12.6. Fractal Synthesis Optimization x
1.12.6.1. Enabling or Disabling Fractal Synthesis
1.14. Viewing Quartus Database File Information x
1.14.1. QDB File Attribute Types
1.15. Understanding the Design Netlist Infrastructure x
1.15.1. DNI Netlist Five-Box Data Model
1.15.1. DNI Netlist Five-Box Data Model x
1.15.1.1. Use Case Examples
1.15.1.1. Use Case Examples x
1.15.1.1.1. Scripting Routine Tasks Using Tcl Commands 1.15.1.1.2. Traversing the Design Netlist Using Tcl Commands
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files x
1.16.1. Registering the SDC-on-RTL SDC File 1.16.2. Applying the SDC-on-RTL Constraints 1.16.3. Inspecting SDC-on-RTL Constraints 1.16.4. Creating Constraints in SDC-on-RTL SDC Files 1.16.5. Using Entity-Based SDC-on-RTL Constraints 1.16.6. Types of SDC Files Used in the Quartus® Prime Software
1.16.4. Creating Constraints in SDC-on-RTL SDC Files x
1.16.4.1. Example: Using SDC-on-RTL Features
1.16.4.1. Example: Using SDC-on-RTL Features x
1.16.4.1.1. SDC-on RTL Example: Targeting Pins of Top-level Instances 1.16.4.1.2. SDC-on RTL Example: Targeting Pins in Cells 1.16.4.1.3. SDC-on RTL Example: Targeting Pins Using Wildcards 1.16.4.1.4. SDC-on RTL Example: Applying Constraints at Deeper Hierarchies
1.16.5. Using Entity-Based SDC-on-RTL Constraints x
1.16.5.1. Entity-based SDC-on-RTL Constraints Example
1.17. Using the Node Finder x
1.17.1. Node Finder Settings Reference
1.18. Synthesis Language Support x
1.18.1. Verilog and SystemVerilog Synthesis Support 1.18.2. VHDL Synthesis Support
1.18.1. Verilog and SystemVerilog Synthesis Support x
1.18.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.18.1.2. Design Libraries 1.18.1.3. Verilog HDL Configuration 1.18.1.4. Initial Constructs and Memory System Tasks 1.18.1.5. Verilog HDL Macros
1.18.1.3. Verilog HDL Configuration x
1.18.1.3.1. Hierarchical Design Configurations
1.18.2. VHDL Synthesis Support x
1.18.2.1. VHDL Input Settings (Settings Dialog Box) 1.18.2.2. VHDL Standard Libraries and Packages 1.18.2.3. VHDL wait Constructs 1.18.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.19. Synthesis Settings Reference x
1.19.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Strategies to Reduce the Overall Compilation Time 2.3. Reducing Synthesis Time 2.4. Reducing Placement Time 2.5. Reducing Routing Time 2.6. Reducing Static Timing Analysis Time 2.7. Setting Process Priority 2.8. Reducing Compilation Time Revision History
2.2. Strategies to Reduce the Overall Compilation Time x
2.2.1. Compilation on a Compute Farm 2.2.2. Enabling Multi-Processor Compilation 2.2.3. Running the ECO Compilation Flow 2.2.4. Using Block-Based Compilation
2.2.2. Enabling Multi-Processor Compilation x
2.2.2.1. Processor Base Clock Frequency 2.2.2.2. Random Access Memory (RAM) 2.2.2.3. Storage
2.3. Reducing Synthesis Time x
2.3.1. Using Precompiled Component Generation 2.3.2. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.3.3. Use Appropriate Coding Style to Reduce Synthesis Time
2.3.1. Using Precompiled Component Generation x
2.3.1.1. Enabling Precompiled Components Generation 2.3.1.2. Precompiled Component Generation Flow
2.4. Reducing Placement Time x
2.4.1. Placement Effort Multiplier Settings
2.5. Reducing Routing Time x
2.5.1. Identifying Routing Congestion 2.5.2. Changing Fitter Aggressive Routability Optimization Settings
2.5.1. Identifying Routing Congestion x
2.5.1.1. Identifying Congestion with the Global Router Congestion Hotspot Summary Report and the Global Router Wire Utilization Map 2.5.1.2. Identifying Routing Congestion with the Chip Planner
Answers to Top FAQs
1. Design Compilation
2. Reducing Compilation Time
3. Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Quartus® Prime Pro Edition User Guides

1.3.3. Post-Synthesis Static Timing Analysis (STA)

Post-synthesis static timing analysis (STA) allows you to run the Timing Analyzer directly after synthesis. This flow involves running Analysis & Elaboration and Synthesis stages and iterating on your design's static timing analysis results early in the Quartus® Prime software compilation flow without running the Fitter.

Figure 37. Early Timing Analysis Flow

The Synopsys* Design Constraint (SDC) on RTL supports the underlying technology to read the constraints early in the compilation flow and use them in the later stages of the Quartus® Prime compilation. However, you can run the flow even without RTL SDCs where you can view the synthesized timing netlist.

Post-synthesis STA defaults to a simple average value delay model based on the types of blocks a net connects. "Average Value" interconnect (IC) delay model to control STA after synthesis. Using the STA_POST_SYN_DELAY_MODEL QSF, you can switch to the "Zero Value" IC delay model to exclude interconnect delays from the timing model.

Note: If you want zero delays, you can also use create_timing_netlist -zero_ic_delay argument.

You can now access the Timing Analyzer right after design synthesis in the compilation dashboard, as shown in the following image:

Figure 38. Early Timing Analysis Stage

Post-synthesis static timing analysis (STA) uses a timing netlist representing core blocks and their contents. It also includes periphery blocks (but nothing inside them is modeled) and cell delays of the core blocks. Routing delays between core blocks is represented by IC delays that use the average interconnect model mentioned above.

Post-synthesis STA timing netlist provides you with an early view of your design's core timing. You can run timing analysis reports and constraint diagnostic commands, allowing you to examine SDC-on-RTL constraints.

Perform the following steps to run post-synthesis STA:

  1. Create an Quartus® Prime software project using your design RTL and associated SDC-on-RTL SDC file.
  2. Run Analysis and Elaboration compilation stage on your design as follows:
    quartus_syn --analysis_and_elaboration <design>
  3. Perform Synthesis on your design as follows: 
    quartus_syn -–synthesis <design>

You can also perform the above steps using the Quartus® Prime software GUI, as shown in the following image:

Figure 39. Performing Post-synthesis STA in the Quartus® Prime Software GUI

After running post-synthesis STA on your design, you can use the Timing Analyzer conventionally. However, a fundamental difference in the netlist topography is that the post-synthesis STA timing netlist has no connectivity inside any periphery block.

Note: The post-synthesis STA delay model defaults to a simple average value delay model. Cell delays are computed assuming default configurations.

For post-synthesis constraints, Intel recommends using an SDC-on-RTL file. In cases where this is not possible, post-synthesis STA introduces the SDC_FILE -read_during_post_syn_and_not_post_fit_timing_analysis QSF argument, which is used to inform the Timing Analyzer to include a conventional SDC in the list of SDCs to be read during a post-synthesis STA session. This QSF is beneficial for blocks that do not have SDC-on-RTL constraints available. Since the post-synthesis STA netlist differs from the post-plan STA netlist, conventional SDCs written for the post-plan netlist might not function during post-synthesis STA. By creating a new category of SDC files, you can identify scripts you want to load during post-synthesis STA.

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