Visible to Intel only — GUID: goq1717714982197
Ixiasoft
1.1. Compilation Overview
1.2. Using the Node Finder
1.3. Design Analysis & Elaboration
1.4. Design Synthesis
1.5. Design Place and Route
1.6. Incremental Optimization Flow
1.7. Fast Forward Compilation Flow
1.8. Full Compilation Flow
1.9. HSSI Dual Simplex IP Generation Flow
1.10. Exporting Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Synthesis Language Support
1.15. Synthesis Settings Reference
1.16. Fitter Settings Reference
1.17. Design Compilation Revision History
1.4.3.1. Registering the SDC-on-RTL SDC File
1.4.3.2. Applying the SDC-on-RTL Constraints
1.4.3.3. Inspecting SDC-on-RTL Constraints
1.4.3.4. Creating Constraints in SDC-on-RTL SDC Files
1.4.3.5. Using Entity-Based SDC-on-RTL Constraints
1.4.3.6. Types of SDC Files Used in the Quartus® Prime Software
1.4.3.7. Example: Using SDC-on-RTL Features
1.10.1. Exporting a Version-Compatible Compilation Database
1.10.2. Importing a Version-Compatible Compilation Database
1.10.3. Creating a Design Partition
1.10.4. Exporting a Design Partition
1.10.5. Reusing a Design Partition
1.10.6. Viewing Quartus Database File Information
1.10.7. Clearing Compilation Results
1.12.1. Compiler Optimization Modes
1.12.2. Precompiled Component (PCC) Generation Stage
1.12.3. Compilation on a Compute Farm
1.12.4. Allow Register Retiming
1.12.5. Automatic Gated Clock Conversion
1.12.6. Enable Intermediate Fitter Snapshots
1.12.7. Fast Preserve Option
1.12.8. Fractal Synthesis Optimization
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time and Synthesis Netlist Optimization Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
Visible to Intel only — GUID: goq1717714982197
Ixiasoft
1.9. HSSI Dual Simplex IP Generation Flow
For designs with supported HSSI IP targeting Agilex™ 5 FPGAs only, you can create and view dual simplex logical assignments according to your channel arrangement. After defining dual simplex groups in the DS Assignment Editor, you run the HSSI Dual Simplex IP Generation stage of the Compiler to generate the dual simplex IP for synthesis. To use DS Assignment Editor to assign DS groups and run HSSI Dual Simplex IP Generation, follow these steps:
- Open a Quartus® Prime Pro Edition project that targets the Agilex™ 5 device and includes a Platform Designer system that contains HSSI IP that support dual simplex mode.
- In Compilation Dashboard, click the IP Generation stage. The Messages window reports when generation is complete.
Figure 113. IP Generation Stage in Compilation Dashboard
- Click Assignments > Dual Simplex (DS) Assignment Editor. The DS Assignment Editor opens listing all supported dual simplex IP in your design in the IP List and any existing DS assignments under DS Groups.
Figure 114. DS Assignment Editor Before Creating DS Groups
- Create dual simplex groups and assign IP instances in DS Assignment Editor:
- Right-click any instance under IP List and click Create instance in > New DS group.
- Double-click the Name cell under DS Groups and type a new group name.
- Right-click the DS Groups row and select Create DS Group.
- Double-click any DS Group name to specify a unique DS group name that becomes the module name for the Verilog output.
Figure 115. Dual Simplex (DS) Assignment Editor
- To place instances in a DS group, right-click the instance name and click Move to group. The visualizer shows the assigned channels and indicates any illegal assignments.
- Under Loopback Mode, double-click in the cell to optionally enable an available loopback mode for debug. NO_LOOPBACK is the default setting.
Figure 116. Available Loopback Modes
- For any IP instance, double-click the Name cell to optionally specify a new instance name for the IP, and a Relative Offset from the origin location in units of channels.
- To specify shared clock properties within a DS group, select the instance under DS Groups, turn on Shared Clock, and specify the IP Port and Merge Port
Figure 117. Specifying Shared Clock Properties
- View the DS assignments in the visualizer display of the Current Group. The visualizer and the Message panel indicate any illegal assignments. The visualizer display shows two rectangles that represent the simplex IP in two channels. These rectangles represent the Tx and Rx channels, respectively. You can select the Current Group that you want to visualize. Illegal assignments appear with red shading in the rectangle, and an error message displays in the Message panel.
Figure 118. Illegal DS Group Assignment in the Assignment Visualizer
- When your DS assignments are complete, click the Save Assignments button to save the DS assignments to the .qsf for application during subsequent compilation stages.
- In the Compilation Dashboard, click HSSI Dual Simplex IP Generation to generate the dual simplex IP.
Figure 119. HSSI Dual Simplex IP Generation Stage in Compilation Dashboard
Note: HSSI Dual Simplex IP Generation is present in Compilation Dashboard only when targeting Agilex™ 5 FPGAs. For more information about dual simplex mode, refer to GTS Transceiver Dual-Simplex Interfaces User Guide.
Related Information