Visible to Intel only — GUID: joc1463161448042
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: joc1463161448042
Ixiasoft
Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | Dedicated reference clock pin | CML, Differential LVPECL, LVDS, and HCSL | |||
RX reference clock pin | CML, Differential LVPECL, and LVDS | ||||
Input Reference Clock Frequency (CMU PLL) |
50 | — | 800 | MHz | |
Input Reference Clock Frequency (ATX PLL) |
100 | — | 800 | MHz | |
Input Reference Clock Frequency (fPLL) |
50 78 | — | 800 | MHz | |
Rise time | 20% to 80% | — | — | 350 | ps |
Fall time | 80% to 20% | — | — | 350 | ps |
Duty cycle | — | 45 | — | 55 | % |
Spread-spectrum modulating clock frequency | PCIe | 30 | — | 33 | kHz |
Spread-spectrum downspread | PCIe | — | 0 to –0.5 | — | % |
On-chip termination resistors | — | — | 100 | — | Ω |
Absolute VMAX | Dedicated reference clock pin | — | — | 1.6 | V |
RX reference clock pin | — | — | 1.2 | V | |
Absolute VMIN | — | –0.4 | — | — | V |
Peak-to-peak differential input voltage | — | 200 | — | 1600 | mV |
VICM (AC coupled) | VCCR_GXB =1.03 V | — | 0 | — | V |
VICM (DC coupled) | HCSL I/O standard for PCIe reference clock | 250 | — | 550 | mV |
Transmitter REFCLK Phase Noise (800 MHz) 79 | 100 Hz | — | — | –70 | dBc/Hz |
1 kHz | — | — | –90 | dBc/Hz | |
10 kHz | — | — | –100 | dBc/Hz | |
100 kHz | — | — | –110 | dBc/Hz | |
≥ 1 MHz | — | — | –120 | dBc/Hz | |
RREF | — | 2.0 k ±1% | — | 2.0 k ±1% | Ω |
TSSC-MAX-PERIOD-SLEW | Max spread spectrum clocking (SSC) df/dt | 0.75 |
Note: When using PCI Express, you must meet the reference clock phase jitter requirements as specified in the 4.3.7 Refclk Specifications for 2.5 GT/s and 5.0 GT/s and 4.3.8 Refclk Specification for 8.0 GT/s sections of the PCI Express Base Specification Revision 3.0.
Clock Network | Maximum Performance 80 | Channel Span | Unit | ||
---|---|---|---|---|---|
ATX | fPLL | CMU | |||
x1 | 17.4 | 12.5 | 10.3125 | 6 channels | Gbps |
x6 | 17.4 | 12.5 | N/A | 6 channels | Gbps |
x24 | 17.4 84 | 12.5 | N/A | 2 banks up and 1 bank down (total 24 channels) or 2 banks down and 1 bank up (total 24 channels) |
Gbps |
GXT clock lines | 26.6 | N/A | N/A | 4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. 81 | Gbps |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O, CML, Differential LVPECL, and LVDS | |||
Absolute VMAX for a receiver pin 82 | — | — | — | 1.2 | V |
Absolute VMIN for a receiver pin 82 83 | — | -0.4 | — | — | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration | — | — | — | 2.0 | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration | VCCR_GXB = 1.03 V 84 | — | — | 2.0 | V |
VCCR_GXB = 1.12 V | — | — | 1.8 | V | |
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VICM (AC coupled) | VCCR_GXB = 1.03 V | — | 700 | — | mV |
VCCR_GXB = 1.12 V | — | 750 | — | mV | |
tLTR 85 | — | — | — | 1 | ms |
tLTD 86 | — | 4 | — | — | µs |
tLTD_manual 87 | — | 4 | — | — | µs |
tLTR_LTD_manual 88 | — | 15 | — | — | µs |
Run Length | — | — | — | 200 | UI |
CDR ppm tolerance | PCIe-only | -300 | — | 300 | ppm |
All other protocols | -1000 | — | 1000 | ppm |
Symbol/Description | Condition | Transceiver Speed Grade 2 and 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O 89 | — | ||
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VOCM (AC coupled) | VCCT_GXB = 1.03 V | — | 515 | — | mV |
Rise time 90 | 20% to 80% | 20 | — | 130 | ps |
Fall time 90 | 80% to 20% | 20 | — | 130 | ps |
Intra-differential pair skew | TX VCM = 0.5 V and slew rate of 15 ps | — | — | 15 91 | ps |
Symbol | VOD Setting 92 | VOD/VCCT_GXB Ratio |
---|---|---|
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB | 31 | 1.00 |
30 | 0.97 | |
29 | 0.93 | |
28 | 0.90 | |
27 | 0.87 | |
26 | 0.83 | |
25 | 0.80 | |
24 | 0.77 | |
23 | 0.73 | |
22 | 0.70 | |
21 | 0.67 | |
20 | 0.63 | |
19 | 0.60 | |
18 | 0.57 | |
17 | 0.53 | |
16 | 0.50 | |
15 | 0.47 | |
14 | 0.43 | |
13 | 0.40 | |
12 | 0.37 |
|
Clock | Value | Unit |
---|---|---|
reconfig_clk | ≤ 150 | MHz |
fixed_clk for the RX detect circuit | 250 ± 20% | MHz |
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
78 The fMIN is 25 MHz when the fPLL is used for the HDMI protocol.
79 To calculate the REFCLK phase noise requirement at frequencies other than 800 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 800 MHz + 20*log(f/800).
80 The maximum data rate depends on speed grade.
81 If the upper ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank above. If the lower ATX PLL in a bank is used as the main GXT PLL, then the channel span includes two GXT channels from the bank below.
82 The device cannot tolerate prolonged operation at this absolute maximum.
83 A passive pull up resistance prevents a 0-V common mode voltage on AC coupled receiver pins before the FPGA is configured.
84 Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For a given L-Tile, if there are channels that need the higher power supply, tie all the channels on that side to the higher power supply.
85 tLTR is the time required for the receiver CDR to lock to the input reference clock frequency after coming out of reset, or after the CDR's calibration is complete.
86 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
87 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.
88 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.
89 High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel® Stratix® 10 L-/H-Tile transceivers.
90 The Intel® Quartus® Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
91 This specification pertains to Hyper Memory Cube.
92 Intel recommends a VOD ranging from 31 to 17.
93 500 ps is not supported for all configurations and depends upon the Master CGB placement.