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Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: bdv1473357395883
Ixiasoft
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices
Symbol | Description | Transceiver Speed Grade | ||
---|---|---|---|---|
-1 | -2 | -3 | ||
GX channels | Chip-to-chip and Backplane | 17.4 Gbps | ||
GXT channels | Chip-to-chip and Backplane | 28.3 Gbps 94 | 26.6 Gbps | N/A |
Note: Refer to the Transceiver Power Supply Operating Conditions for VCCR_GXB and VCCT_GXB specifications when using bonded and non-bonded transceiver channels in Intel® Stratix® 10 H-Tile devices.
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Transceiver Speed Grade 3 | Unit |
---|---|---|---|---|---|
Supported Output Frequency | Maximum Frequency | 14.15 | 13.3 | 8.7 | GHz |
Minimum Frequency | 500 | MHz | |||
tLOCK 95 | Maximum Frequency | 1 | ms | ||
tARESET 96 | — | 25 | Avalon Clock Cycles |
Note: TX jitter specifications for the SerialLite III protocol at 17.4 Gbps are as low as: TJ = 0.32 UI, RJ = 0.15 UI, DJ = 0.18 UI, and DCD = 0.05 UI.
Symbol/Description | Condition | Mode | All Transceiver Speed Grades | Unit |
---|---|---|---|---|
Supported Output Frequency (VCO frequency based) | Maximum datarate | Transceiver - HDMI | 12.5 | Gbps |
Transceiver - General | 12.5 | |||
Transceiver - OTN, SDI Cascade | 14.025 | |||
Minimum datarate | Transceiver - HDMI | 4.6 | Gbps | |
Transceiver - General | 6 | |||
Transceiver - OTN, SDI Cascade | 7 | |||
tLOCK 95 | Maximum Frequency | 1 | ms | |
tARESET 96 | — | 25 | Avalon Clock Cycles |
94 Only four GXT channels per bank are supported for backplane applications operating at 28.3 Gbps.
95 This specification applies after the ATX PLL, fPLL, or CMU PLL has completed calibration.
96 You must use the Avalon-MM interface to hold the PLLs in reset for the specified cycles by writing to the ATX PLL, fPLL, or CMU PLL pll_powerdown register.