Visible to Intel only — GUID: mcn1441702555198
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: mcn1441702555198
Ixiasoft
Differential SSTL I/O Standards Specifications
I/O Standard | VCCIO (V) | VSWING(DC) (V) | VSWING(AC) (V) | VIX(AC) (V) | ||||||
---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.25 | VCCIO + 0.6 | 0.5 | VCCIO + 0.6 | VCCIO/2 – 0.175 | — | VCCIO/2 + 0.175 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | 37 | 2(VIH(AC) – VREF) | 2(VREF – VIL(AC)) | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 |
SSTL-135 | 1.283 | 1.35 | 1.45 | 0.18 | 37 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 |
SSTL-125 | 1.19 | 1.25 | 1.31 | 0.18 | 37 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | — | VCCIO/2 + 0.15 |
SSTL-12 | 1.14 | 1.2 | 1.26 | 0.16 | 37 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VREF – 0.15 | VCCIO/2 | VREF + 0.15 |
37 The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (VIH(DC) and VIL(DC)).