Intel® Stratix® 10 Device Datasheet

Download PDF
ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices

Table 73.  P-Tile Transmitter and Receiver Data Rate Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition Gen 1 Gen 2 Gen 3 Gen 4 Unit
Supported data rate124 PCIe* 2.5 5 8 16 Gbps
Table 74.  P-Tile PLLA Performance For specification status, see the Data Sheet Status table
Symbol/Description Condition Min Typ Max Unit
VCO frequency PCIe* — 5 — GHz
Intel® UPI uwk1553212023175.html#uwk1553212023175__fn_apll-f1 — 5.2 — GHz
PLL bandwidth (BWTX_PKG_PLL1) 125 PCIe* 2.5 GT/s 1.5 — 22 MHz
PCIe* 5.0 GT/s 8 — 16 MHz
PLL bandwidth (BWTX_PKG_PLL2)125 PCIe* 5.0 GT/s 5 — 16 MHz
PLL peaking (PKGTX_PLL1) PCIe* 2.5 GT/s — — 3 dB
PCIe* 5.0 GT/s — — 3 dB
PLL peaking (PKGTX_PLL2)125 PCIe* 5.0 GT/s 1 — — dB
Table 75.  P-Tile PLLB Performance For specification status, see the Data Sheet Status table. PLLB is not used for the UPI mode.
Symbol/Description Condition Min Typ Max Unit
VCO frequency PCIe* — 8 — GHz
PLL bandwidth (BWTX-PKG_PLL1) 126 PCIe* 8.0 GT/s 2 — 4 MHz
PCIe* 16.0 GT/s 2 — 4 MHz
PLL bandwidth (BWTX-PKG_PLL2)126 PCIe* 8.0 GT/s 2 — 5 MHz
PCIe* 16.0 GT/s 2 — 5 MHz
PLL peaking (PKGTX-PLL1)126 PCIe* 8.0 GT/s — — 2 dB
PCIe* 16.0 GT/s — — 2 dB
PLL peaking (PKGTX-PLL2)126 PCIe* 8.0 GT/s — — 1 dB
PCIe* 16.0 GT/s — — 1 dB
124 Intel® Ultra Path Interconnect ( Intel® UPI) supports chip-to-chip and low-loss cable up to 10.4 Gbps.
125 The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.
126 The Tx PLL bandwidth must lie between the minimum and maximum ranges given in this table. PLL peaking must lie below the value in this table. Note that the PLL bandwidth extends from zero up to the values specified in this table. The PLL bandwidth is defined at the point where its transfer function crosses the –3 dB point.
Level Two Title