Intel® Stratix® 10 Device Datasheet

ID 683181
Date 12/08/2023
Public
Document Table of Contents

HPS NAND Timing Characteristics

Table 95.  HPS NAND ONFI 1.0 Timing Requirements for Intel® Stratix® 10 Devices
Symbol Description Min Max Unit
TWP 159 Write enable pulse width 10 ns
TWH 159 Write enable hold time 7 ns
TRP 159 Read enable pulse width 10 ns
TREH 159 Read enable hold time 7 ns
TCLS 159 Command latch enable to write enable setup time 10 ns
TCLH 159 Command latch enable to write enable hold time 5 ns
TCS 159 Chip enable to write enable setup time 15 ns
TCH 159 Chip enable to write enable hold time 5 ns
TALS 159 Address latch enable to write enable setup time 10 ns
TALH 159 Address latch enable to write enable hold time 5 ns
TDS 159 Data to write enable setup time 7 ns
TDH 159 Data to write enable hold time 5 ns
TWB 159 Write enable high to R/B low 200 ns
TCEA Chip enable to data access time 100 ns
TREA Read enable to data access time 40 ns
TRHZ Read enable to data high impedance 200 ns
TRR Ready to read enable low 20 ns
Figure 18. NAND Command Latch Timing Diagram
Figure 19. NAND Address Latch Timing Diagram
Figure 20. NAND Data Output Cycle Timing Diagram
Figure 21. NAND Data Input Cycle Timing Diagram
Figure 22. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 23. NAND Read Status Timing Diagram
Figure 24. NAND Read Status Enhanced Timing Diagram
159 This timing is software programmable. Refer to the NAND Flash Controller chapter in the Stratix 10 Hard Processor System Technical Reference Manual for more information about software-programmable timing in the NAND flash controller.