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Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
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HPS NAND Timing Characteristics
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
TWP 159 | Write enable pulse width | 10 | — | ns |
TWH 159 | Write enable hold time | 7 | — | ns |
TRP 159 | Read enable pulse width | 10 | — | ns |
TREH 159 | Read enable hold time | 7 | — | ns |
TCLS 159 | Command latch enable to write enable setup time | 10 | — | ns |
TCLH 159 | Command latch enable to write enable hold time | 5 | — | ns |
TCS 159 | Chip enable to write enable setup time | 15 | — | ns |
TCH 159 | Chip enable to write enable hold time | 5 | — | ns |
TALS 159 | Address latch enable to write enable setup time | 10 | — | ns |
TALH 159 | Address latch enable to write enable hold time | 5 | — | ns |
TDS 159 | Data to write enable setup time | 7 | — | ns |
TDH 159 | Data to write enable hold time | 5 | — | ns |
TWB 159 | Write enable high to R/B low | — | 200 | ns |
TCEA | Chip enable to data access time | — | 100 | ns |
TREA | Read enable to data access time | — | 40 | ns |
TRHZ | Read enable to data high impedance | — | 200 | ns |
TRR | Ready to read enable low | 20 | — | ns |
Figure 18. NAND Command Latch Timing Diagram
Figure 19. NAND Address Latch Timing Diagram
Figure 20. NAND Data Output Cycle Timing Diagram
Figure 21. NAND Data Input Cycle Timing Diagram
Figure 22. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 23. NAND Read Status Timing Diagram
Figure 24. NAND Read Status Enhanced Timing Diagram
Related Information
159 This timing is software programmable. Refer to the NAND Flash Controller chapter in the Stratix 10 Hard Processor System Technical Reference Manual for more information about software-programmable timing in the NAND flash controller.