Visible to Intel only — GUID: jnt1492147870823
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: jnt1492147870823
Ixiasoft
Glossary
Term | Definition |
---|---|
Differential I/O Standards | Receiver Input Waveforms
Transmitter Output Waveforms
|
fHSCLK | I/O PLL input clock frequency. |
fHSDR | High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. |
fHSDRDPA | High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. |
J | High-speed I/O block—Deserialization factor (width of parallel data bus). |
JTAG Timing Specifications | JTAG Timing Specifications:
|
RL | Receiver differential input discrete resistor (external to the Intel® Stratix® 10 device). |
Sampling window (SW) | Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown:
|
Single-ended voltage referenced I/O standard | The JEDEC* standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard
|
tC | High-speed receiver/transmitter input and output clock period. |
TCCS (channel-to-channel-skew) | The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). |
tDUTY | High-speed I/O block—Duty cycle on high-speed transmitter output clock. |
tFALL | Signal high-to-low transition time (80–20%). |
tINCCJ | Cycle-to-cycle jitter tolerance on the PLL clock input. |
tOUTPJ_IO | Period jitter on the GPIO driven by a PLL. |
tOUTPJ_DC | Period jitter on the dedicated clock output driven by a PLL. |
tRISE | Signal low-to-high transition time (20–80%). |
Timing Unit Interval (TUI) | The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w). |
VCM(DC) | DC Common mode input voltage. |
VICM | Input Common mode voltage—The common mode of the differential signal at the receiver. |
VICM(DC) | VCM(DC) DC Common mode input voltage. |
VID | Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. |
VDIF(AC) | AC differential input voltage—Minimum AC input differential voltage required for switching. |
VDIF(DC) | DC differential input voltage— Minimum DC input differential voltage required for switching. |
VIH | Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high. |
VIH(AC) | High-level AC input voltage. |
VIH(DC) | High-level DC input voltage. |
VIL | Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low. |
VIL(AC) | Low-level AC input voltage. |
VIL(DC) | Low-level DC input voltage. |
VOCM | Output Common mode voltage—The common mode of the differential signal at the transmitter. |
VOD | Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. |
VSWING | Differential input voltage. |
VOX | Output differential cross point voltage. |
VIX(AC) | Crossing point of differential signal
|
W | High-speed I/O block—Clock Boost Factor. |