Visible to Intel only — GUID: mcn1441099948103
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Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: mcn1441099948103
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Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel® Stratix® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.
CAUTION:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Symbol | Description | Condition | Minimum | Maximum | Unit |
---|---|---|---|---|---|
VCC | Core voltage power supply | — | –0.50 | 1.26 | V |
VCCP | Periphery circuitry and transceiver fabric interface power supply | — | –0.50 | 1.26 | V |
VCCERAM | Embedded memory and digital transceiver power supply | — | –0.50 | 1.24 | V |
VCCPT | Power supply for programmable regulator and I/O pre-driver | — | –0.50 | 2.46 | V |
VCCBAT | Battery back-up power supply for design security volatile key register | — | –0.50 | 2.46 | V |
VCCIO_SDM | Configuration pins power supply | — | –0.50 | 2.19 | V |
VCCIO | I/O buffers power supply (except for 1SG040HF35 and 1SX040HF35 banks 3C and 3D) | 3 V I/O | –0.50 | 4.10 | V |
LVDS I/O 1 | –0.50 | 2.19 | V | ||
VCCIO3C | I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3C only | — | –0.50 | 3.63 | V |
VCCIO3D | I/O buffers power supply for 1SG040HF35 and 1SX040HF35 devices bank 3D only | — | –0.50 | 1.98 | V |
VCCA_PLL | Phase-locked loop (PLL) analog power supply | — | –0.50 | 2.46 | V |
VCCPLLDIG_SDM | Secure Device Manager (SDM) block PLL digital power supply | — | –0.50 | 1.21 | V |
VCCPLL_SDM | SDM block PLL analog power supply | — | –0.50 | 2.19 | V |
VCCFUSEWR_SDM | Fuse block writing power supply | — | –0.50 | 3.19 | V |
VCCADC | ADC voltage sensor power supply | — | –0.50 | 2.19 | V |
VCCIO_UIB | Power supply for the Universal Interface Bus between the core and embedded HBM2 memory | — | –0.30 | 1.50 | V |
VCCM_WORD | Power supply for the embedded HBM2 memory | — | –0.30 | 3.00 | V |
VCCT_GXB | Transmitter analog power supply | — | –0.50 | 1.47 | V |
VCCR_GXB | Receiver analog power supply | — | –0.50 | 1.47 | V |
VCCH_GXB | Transmitter output buffer power supply | — | –0.50 | 2.46 | V |
VCCRT_GXE | E-tile transceiver power supply | — | –0.50 | 1.21 | V |
VCCRTPLL_GXE | E-tile transceiver PLL power supply | — | –0.50 | 1.21 | V |
VCCH_GXE | E-tile transceiver analog power supply | — | –0.50 | 1.47 | V |
VCCCLK_GXE | E-tile transceiver LVPECL REFCLK power supply | — | –0.50 | 3.41 | V |
VCCRT_GXP | P-tile transceiver power supply | — | –0.50 | 1.21 | V |
VCCFUSE_GXP | P-tile transceiver eFuse power supply | — | –0.50 | 1.21 | V |
VCCH_GXP | P-tile transceiver analog power supply | — | –0.50 | 2.46 | V |
VCCCLK_GXP | P-tile transceiver I/O buffer power supply | — | –0.50 | 2.46 | V |
VCCL_HPS | HPS core voltage and periphery circuitry power supply | — | –0.50 | 1.30 | V |
VCCIO_HPS | HPS I/O buffers power supply | LVDS I/O 1 | –0.50 | 2.19 | V |
VCCPLL_HPS | HPS PLL power supply | — | –0.50 | 2.46 | V |
VI | DC input voltage | 3.3 V I/O | –0.30 | VCCIO + 0.33 | V |
3 V I/O | –0.30 | VCCIO + 0.65 | V | ||
LVDS I/O | –0.30 | VCCIO + 0.3 | V | ||
IOUT | DC output current per pin | — | –15 2 3 4 5 6 | 15 | mA |
TJ | Absolute junction temperature for Intel® Stratix® 10 MX, NX, and DX 2100 devices | — | –55 | 120 | °C |
Absolute junction temperature for Intel® Stratix® 10 GX 10M device | — | 0 | 125 | °C | |
Absolute junction temperature for all other Intel® Stratix® 10 devices | — | –55 | 125 | °C | |
TSTG | Storage temperature (no bias) for Intel® Stratix® 10 MX, NX, and DX 2100 devices | — | –55 | 120 | °C |
Storage temperature (no bias) for Intel® Stratix® 10 GX 10M device | — | 0 | 125 | °C | |
Storage temperature (no bias) for all other Intel® Stratix® 10 devices | — | –55 | 150 | °C |
1 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
2 The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA.
3 Total current per LVDS I/O bank must not exceed 100 mA.
4 Voltage level must not exceed 1.89 V.
5 Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os.
6 Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power sequencing requirement. For more details, refer to AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 Devices and Intel® Stratix® 10 Power Management User Guide.