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Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: kdo1492708358426
Ixiasoft
HPS SPI Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tspi_ref_clk | The period of the SPI internal reference clock, sourced from l4_main_clk | 2.5 | — | — | ns |
Tclk | SPIM_CLK clock period | 16.67 | — | — | ns |
Tdutycycle | SPIM_CLK duty cycle | 45 | 50 | 55 | % |
Tck_jitter | SPIM_CLK output jitter | — | — | 2 | % |
Tdio | Master-out slave-in (MOSI) output skew | –3 | — | 2 | ns |
Tdssfrst 140 | SPI_SS_N asserted to first SPIM_CLK edge | (1.5 × Tclk) – 2 | — | — | ns |
Tdsslst 140 | Last SPIM_CLK edge to SPI_SS_N deasserted | Tclk – 2 | — | — | ns |
Tsu 141 | SPIM_MISO setup time with respect to SPIM_CLK capture edge | 4.5 – (rx_sample_dly × T spi_ref_clk) 142 | — | — | ns |
Th 141 | Input hold in respect to SPIM_CLK capture edge | 1.3 + (rx_sample_dly× Tspi_ref_clk) | — | — | ns |
Figure 7. SPI Master Output Timing Diagram
Figure 8. SPI Master Input Timing Diagram
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Tspi_ref_clk | The period of the SPI internal reference clock, sourced from l4_main_clk | 2.5 | — | — | ns |
Tclk | SPIM_CLK clock period | 30 | — | — | ns |
Tdutycycle | SPIM_CLK duty cycle | 45 | 50 | 55 | % |
Td | Master-in slave-out (MISO) output skew | (2 × Tspi_ref_clk) + 3 | — | (3 × Tspi_ref_clk) + 11 | ns |
Tsu | Master-out slave-in (MOSI) setup time | 4 | — | — | ns |
Th | Master-out slave-in (MOSI) hold time | 9 | — | — | ns |
Tsuss | SPI_SS_N asserted to first SPIM_CLK edge | Tspi_ref_clk + 4 | — | — | ns |
Thss | Last SPIM_CLK edge to SPI_SS_N deasserted | Tspi_ref_clk + 4 | — | — | ns |
Figure 9. SPI Slave Output Timing Diagram
Figure 10. SPI Slave Input Timing Diagram
Related Information
140 SPI_SS_N behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
141 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.
142 Valid values of rx_sample_dly range from 1 to 64 (units are in T spi_ref_clk steps).