Visible to Intel only — GUID: mcn1441706181503
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: mcn1441706181503
Ixiasoft
Fractional PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | — | 29 | — | 800 43 | MHz |
fINPFD | Input clock frequency to the phase frequency detector (PFD) | — | 29 | — | 700 | MHz |
fVCO | PLL voltage-controlled oscillator (VCO) operating range for core applications | — | 6 | — | 14.025 | GHz |
tEINDUTY | Input clock duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal clock | — | — | — | 1 | GHz |
fDYCONFIGCLK | Dynamic configuration clock for reconfig_clk | — | — | — | 125 | MHz |
tLOCK | Time required to lock from end-of-device configuration | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
fCLBW | PLL closed-loop bandwidth | — | 0.3 | — | 4 | MHz |
tINCCJ 44, 45 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.13 | UI (p-p) |
FREF < 100 MHz | — | — | ±650 | ps (p-p) | ||
tOUTPJ 46 | Period jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ 46 | Cycle-to-cycle jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
dKBIT | Bit number of Delta Sigma Modulator (DSM) | — | — | 32 | — | bit |
Related Information
43 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
44 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
45 FREF is fIN/N, specification applies when N = 1.
46 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specifications for Intel® Stratix® 10 Devices table.