Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

Document Revision History for the Intel® Stratix® 10 Device Datasheet

Document Version Changes
2023.12.08
  • Updated the following diagrams:
    • AS Configuration Serial Output Timing Diagram
    • AS Configuration Serial Input Timing Diagram
  • Updated the Device Datasheet topic:
    • Updated datasheet status for all variant to Final in the Datasheet Status for Intel Stratix 10 Devices table. Removed the footnote on the specifications related to Intel Intellectual Property (IP) products, UPI IP, and DDR-T IP are preliminary.
    • Removed a note in the Device Datasheet topic.
  • Added a footnote to Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
  • Removed mentions of GX/SX/MX/TX in Intel® Stratix® 10 H-Tile devices.
    • Updated table title: Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX/MX/TX H-Tile Devices in a Non-Bonded Configuration to Transceiver Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices in a Non-Bonded Configuration.
    • Updated table title: Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX/MX/TX H-Tile Devices in a Bonded Configuration to Transceiver Power Supply Operating Conditions for Intel Stratix 10 H-Tile Devices in a Bonded Configuration.
    • Updated topic title: Transceiver Performance for Intel Stratix 10 GX/SX/MX/TX H-Tile Devices to Transceiver Performance for Intel Stratix 10 H-Tile Devices.
    • Updated table title: Intel Stratix 10 GX/SX/MX/TX H-Tile Transmitter and Receiver Datarate Performance to Intel Stratix 10 H-Tile Transmitter and Receiver Datarate Performance.
    • Updated topic title: Transceiver Specifications for Intel Stratix 10 GX/SX H-Tile Devices to Transceiver Specifications for Intel Stratix 10 H-Tile Devices.
    • Updated table title: Transceiver Clocks Specifications for Intel Stratix 10 GX/SX H-Tile Devices to Transceiver Clocks Specifications for Intel Stratix 10 H-Tile Devices.
  • Removed mentions of GX/SX in Intel® Stratix® 10 L-Tile devices.
    • Updated table title: Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Non-Bonded Configuration to Transceiver Power Supply Operating Conditions for Intel Stratix 10 L-Tile Devices in a Non-Bonded Configuration.
    • Updated table title: Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Bonded Configuration to Transceiver Power Supply Operating Conditions for Intel Stratix 10 L-Tile Devices in a Bonded Configuration.
    • Updated topic title: Transceiver Performance for Intel Stratix 10 GX/SX L-Tile Devices to Transceiver Performance for Intel Stratix 10 L-Tile Devices.
    • Updated table title: Intel Stratix 10 GX/SX L-Tile Transmitter and Receiver Datarate Performance to Intel Stratix 10 L-Tile Transmitter and Receiver Datarate Performance.
    • Updated topic title: Transceiver Specifications for Intel Stratix 10 GX/SX L-Tile Devices to Transceiver Specifications for Intel Stratix 10 L-Tile Devices.
  • Removed mentions of TX/MX in Intel® Stratix® 10 E-Tile devices.
    • Updated table title: Transceiver Power Supply Operating Conditions for Intel Stratix 10 TX/MX E-Tile Devices to Transceiver Power Supply Operating Conditions for Intel Stratix 10 E-Tile Devices.
  • Updated footnote on the data rate for Transceiver Power Supply Operating Conditions for Intel Stratix 10 DX P-Tile Devices table.
  • Added Differential POD12 Standards Specifications for Intel Stratix 10 Devices table.
  • Updated the footnotes in the Differential I/O Standards Specifications for Intel Stratix 10 Devices table.
  • Removed the description for H-Tile Transmitter Specifications table.
  • Removed the footnote for Intel UPI in the P-Tile PLLA Performance table.
  • Updated diagram title in HPS Ethernet Media Access Controller (EMAC) Timing Characteristics topic: RGMII TX and RMII TX Timing Diagram to RGMII TX Timing Diagram.
  • Added a new diagram RMII TX Timing Diagram in HPS Ethernet Media Access Controller (EMAC) Timing Characteristics topic.
  • Updated General Configuration Timing Diagram.
  • Updated table description for AS Timing Parameters for Intel Stratix 10 Devices table.
  • Updated table description for Configuration Bit Stream Sizes for Intel® Stratix® 10 Devices table.
  • Updated Programmable IOE Delay for Intel Stratix 10 Devices table.
2022.01.12
  • Added a note to Simple quad-port, all supported widths mode in the Memory Block Performance Specifications for Intel® Stratix® 10 Devices table.
  • Updated the L-Tile Receiver Specifications table.
    • Added maximum peak-to-peak differential input voltage VID (diff p-p) specifications before device configuration.
    • Updated maximum peak-to-peak differential input voltage VID (diff p-p) specifications after device configuration.
  • Updated the maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration in the H-Tile Receiver Specifications table.
2021.05.24
  • Added specifications for 1SG065 and 1SX065 devices. Removed the note that mentioned about specifications for 1SG065 and 1SX065 devices will be available in a future release.
  • Updated the Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
    • Updated the extended grade minimum TJ specifications for Intel® Stratix® 10 GX 10M device.
    • Added clarity for the industrial grade minimum TJ specifications.
  • Updated the General Configuration Timing Diagram.
  • Updated the AS Timing Parameters for Intel® Stratix® 10 Devices table.
    • Updated Tclk, Tdcsfrs, Tdcslst, Text_delay, and Tdcsb2b specifications.
    • Removed footnote for Tdcsfrs and Tdcslst specifications.
    • Updated the footnote on AS_CLK frequency for Text_delay parameter.
2021.02.22
  • Added the HPS Cold Reset for Intel® Stratix® 10 Devices table.
  • Added tST12CF0 and tST02CF1 specifications in the General Configuration Timing Specifications for Intel® Stratix® 10 Devices table.
  • Added General Configuration Timing Diagram.
  • Changed the status of the General Configuration Timing Specifications for Intel® Stratix® 10 Devices table from Preliminary to Final.
2020.12.24
  • Added Intel® Stratix® 10 NX and DX 2100 devices in the following sections:
    • Absolute Maximum Ratings for Intel® Stratix® 10 Devices table
    • Recommended Operating Conditions for Intel® Stratix® 10 Devices table
    • Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and SD 2100 Devices table
    • HBM2 Interface Performance section
  • Updated the E-Tile Receiver Specifications table.
    • Updated the Absolute VMAX and VCM specifications.
    • Updated the note to VCM.
    • Added note to Absolute VMAX and VID (diff p-p).
  • Updated the P-Tile PLLA Performance table.
    • Added PLL bandwidth (BWTX-PKG_PLL1) and PLL peaking (PKGTX-PLL1) specifications for PCIe 5.0 GT/s.
    • Updated PLL peaking (PKGTX-PLL2) specifications.
    • Added note on PLL bandwidth and PLL peaking.
  • Updated the P-Tile PLLB Performance table.
    • Added PLL bandwidth (BWTX-PKG_PLL2) and PLL peaking (PKGTX-PLL2) specifications.
    • Added note on PLL bandwidth and PLL peaking.
  • Updated the spread-spectrum downspread, absolute VMAX, and absolute VMIN specifications in the P-Tile Reference Clock Specifications table.
  • Updated the differential peak-to-peak voltage for full swing specifications in the P-Tile Transmitter Specifications table.
  • Removed VICM (AC coupled) specifications from the P-Tile Receiver Specifications table.
2020.07.08
  • Added –C2L speed grade in the Intel® Stratix® 10 Device Grades and Speed Grades Supported table.
  • Added a note to mention that the specifications for 1SG065 and 1SX065 devices will be available in a future release.
  • Added TJ and TSTG specifications for Intel® Stratix® 10 GX 10M device in the Absolute Maximum Ratings for Intel® Stratix® 10 Devices table.
  • Updated the Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
    • Added VCC, VCCP, and TJ specifications for Intel® Stratix® 10 GX 10M device.
    • Removed the note on HPS_PORSEL from tRAMP. HPS_PORSEL pin is not available for Intel® Stratix® 10 devices.
  • Updated II_3.3VIO specifications in the I/O Pin Leakage Current for Intel® Stratix® 10 Devices table.
  • Removed specifications for VCCIO = 3.3 ±5% and VCCIO3C = 3.0 ±5% in the Internal Weak Pull-Up Resistor Values for Intel® Stratix® 10 Devices table.
  • Added –C2L speed grade in the following tables:
    • Clock Tree Performance for Intel® Stratix® 10 Devices
    • DSP Block Performance Specifications for Intel® Stratix® 10 Devices
    • Memory Block Performance Specifications for Intel® Stratix® 10 Devices
  • Added the DIB Specifications for Intel® Stratix® 10 GX 10M Device table.
  • Added –C2L speed grade in the High-Speed I/O Specifications for Intel® Stratix® 10 Devices table. Added note to transmitter and receiver –2 speed grade maximum specifications for SERDES factor J = 4 to 10.
  • Updated DDR-T specifications in the Memory Standards Supported by the Soft Memory Controller for Intel® Stratix® 10 Devices table.
  • Added note to Text_delay in the AS Timing Parameters for Intel® Stratix® 10 Devices.
  • Added Intel® Stratix® 10 GX 10M device in the Configuration Bit Stream Sizes for Intel® Stratix® 10 Devices table.
  • Removed SD/MMC configuration mode specifications.
  • Removed Maximum Configuration Time Estimation specifications.
  • Changed Early Power Estimator (EPE) to Intel FPGA Power and Thermal Calculator (PTC).
2020.05.22
  • Changed Intel® Stratix® 10 DX status from Preliminary to Final in the Datasheet Status for Intel® Stratix® 10 Devices table. Added a note to mention that specifications related to Intel Intellectual Property (IP) products, UPI IP, and DDR-T IP are preliminary.
  • Added DDR-T specifications in the Memory Standards Supported by the Soft Memory Controller for Intel® Stratix® 10 Devices table.
  • Updated the specifications in the P-Tile Transmitter and Receiver Data Rate Performance table.
  • Updated VCO frequency in the following tables:
    • P-Tile PLLA Performance
    • P-Tile PLLB Performance
  • Updated the note to Input Reference Clock Frequency in the P-Tile Reference Clock Specifications table.
  • Updated the P-Tile Transmitter Specifications table.
    • Updated the Differential peak-to-peak voltage for full swing specifications.
    • Removed the Differential peak-to-peak voltage for reduced swing and Differential peak-to-peak voltage during EIEOS for reduce swing specifications.
  • Updated the P-Tile Receiver Specifications table.
    • Added VID (diff p-p) PCIe* 8.0 GT/s and PCIe* 16.0 GT/s specifications.
    • Added a note to RESREF.
    • Added RREF specifications.
2020.03.10
  • Mentioned that the specifications for 1SG040HF35 and 1SX040HF35 devices are still preliminary in the Datasheet Status for Intel® Stratix® 10 Devices table.
  • Updated the Absolute Maximum Ratings for Intel® Stratix® 10 Devices table.
    • Added VCCIO3C and VCCIO3D specifications.
    • Updated the description for VCCIO.
    • Added VI specifications for 3.3 V I/O.
  • Added a new table: Maximum Allowed Overshoot During Transitions for Intel® Stratix® 10 Devices (for 3.3 V I/O).
  • Updated the Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
    • Added VCCIO3C, VCCIO3D, and VI (for 3.3 V I/O) specifications.
    • Updated the description for VCCIO.
    • Updated note to TJ specification for Industrial.
  • Added II_3.3VIO specifications in the I/O Pin Leakage Current for Intel® Stratix® 10 Devices table.
  • Added CIO_3.3VIO specifications in the Pin Capacitance for Intel® Stratix® 10 Devices table.
  • Added RPU specifications for 3.3 V I/O in the Internal Weak Pull-Up Resistor Values for Intel® Stratix® 10 Devices table.
  • Added 3.3 V LVTTL, 3.3 V LVCMOS, 3.0 V LVTTL, and 3.0 V LVCMOS specifications for 1SG040HF35 or 1SX040HF35 devices I/O bank 3C only in the Single-Ended I/O Standards Specifications for Intel® Stratix® 10 Devices table.
  • Updated the description in the DPA Lock Time Specifications for Intel® Stratix® 10 Devices table.
  • Added a note to VICM (AC coupled) in the E-Tile Receiver Specifications table.
  • Added specifications for Intel® Stratix® 10 TX 400 devices and updated specifications for Intel® Stratix® 10 GX 400, SX 400, GX 1650, GX 2100, SX 1650, and SX 2100 devices in the following tables:
    • Configuration Bit Stream Sizes for Intel® Stratix® 10 Devices
    • Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices ( Avalon® -ST)
    • Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices (AS and SD/MMC)
2019.12.02
  • Updated the note to VOD in the Differential I/O Standards Specifications for Intel® Stratix® 10 Devices table.
  • Added description on PCIe* applications in the Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices tables.
  • Added specifications for Intel® Stratix® 10 DX devices in the following tables:
    • External Temperature Sensing Diode Specifications for Intel® Stratix® 10 Devices
    • Configuration Bit Stream Sizes for Intel® Stratix® 10 Devices
    • Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices ( Avalon® -ST)
    • Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices (AS and SD/MMC)
    • Programmable IOE Delay for Intel® Stratix® 10 Devices
  • Updated RESREF specification in the P-Tile Receiver Specifications table.
2019.09.19
  • Added Intel® Stratix® 10 DX as Preliminary in the Datasheet Status for Intel® Stratix® 10 Devices table.
  • Updated the definition for the V suffix.
  • Updated the Absolute Maximum Ratings for Intel® Stratix® 10 Devices table.
    • Added E-tile specific power supplies VCCRT_GXE, VCCRTPLL_GXE, VCCH_GXE, and VCCCLK_GXE.
    • Added P-tile specific power supplies VCCRT_GXP, VCCFUSE_GXP, VCCH_GXP, and VCCCLK_GXP.
    • Updated the description for VCCPT.
    • Added specifications for the following power rails:
      • VCCPLLDIG_SDM
      • VCCPLL_SDM
      • VCCFUSEWR_SDM
      • VCCADC
      • VCCIO_UIB
      • VCCM_WORD
    • Updated the maximum specifications for VI.
  • Updated the Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
    • Updated the note on PMBus* for VCC and VCCP.
    • Updated the note for VCCBAT.
    • Updated the description for VCCPT.
    • Updated VCCIO specifications.
    • Added VCCIO3V specifications.
    • Updated the maximum specifications for VI.
    • Updated the note on HBM2 for Intel® Stratix® 10 MX devices for TJ specification.
  • Updated VCCL_HPS and VCCPLLDIG_HPS specifications and note for SmartVID in the HPS Power Supply Operating Conditions for Intel® Stratix® 10 Devices table.
  • Added description on internal weak pull-down resistor in the Internal Weak Pull-Up Resistor section.
  • Split M20K block—ROM, all supported widths specifications into single port and dual port in the Memory Block Performance Specifications for Intel® Stratix® 10 Devices table.
  • Updated the External Temperature Sensing Diode Specifications for Intel® Stratix® 10 Devices table.
    • Added Ibias and Vbias specifications for E-Tile TSD.
    • Updated Ibias specifications for core fabric, L-Tile, and H-Tile TSD.
    • Updated series resistance for core fabric, L-Tile, H-Tile, and E-Tile TSD.
    • Updated diode ideality factor for L-Tile, H-Tile, and E-Tile TSD.
  • Updated the minimum data rates for the receiver fHSDRDPA in the High-Speed I/O Specifications for Intel® Stratix® 10 Devices table.
  • Removed figure: DPA Lock Time Specifications with DPA PLL Calibration Enabled.
  • Updated maximum data transition value and added a note in the DPA Lock Time Specifications for Intel® Stratix® 10 Devices table.
  • Updated the QDR II SRAM specifications in the Memory Standards Supported by the Soft Memory Controller for Intel® Stratix® 10 Devices table.
  • Updated the note in the HBM2 Interface Performance section.
  • Updated the supported output frequency in the H-Tile ATX PLL Performance table.
  • Updated the input reference clock frequency (fPLL) and its note in the H-Tile Reference Clock Specification table.
  • Removed a note from the H-Tile Receiver Specification table.
  • Added a note for VOCM (DC coupled) in the H-Tile Transmitter Specification table.
  • Updated E-Tile Transmitter and Receiver Data Rate Performance Specifications table.
  • Updated the E-Tile Receiver Specifications table.
    • Added Supported I/O Standards specifications.
    • Added Absolute VMAX for a receiver pin specifications.
    • Added Maximum peak-to-peak differential input voltage VID specifications.
    • Added VICM(AC coupled) specifications.
    • Removed the Electrical Idle detection voltage specifications.
  • Added P-Tile Transceiver Performance Specification section.
    • Added P-Tile Transmitter and Receiver Data Rate Performance table.
    • Added P-Tile PLLA Performance table.
    • Added P-Tile PLLB Performance table.
    • Added P-Tile Reference Clock Specifications table.
    • Added P-Tile Transmitter Specifications table.
    • Added P-Tile Receiver Specifications table.
  • Removed description in the HPS GPIO Interface section. Statement removed: Any pulses shorter than 2 debounce clock cycles are filtered by the GPIO peripheral.
  • Updated tCF12ST1, tCF02ST0, tST0, and tCD2UM in the General Configuration Timing Specifications for Intel® Stratix® 10 Devices table.
  • Added a note on P-tile support to the JTAG Timing Parameters and Values for Intel® Stratix® 10 Devices table.
  • Updated the AS Timing Parameters for Intel® Stratix® 10 Devices table.
    • Added notes to Tclk, Tdo, and Text_delay.
    • Updated the description for Tdo.
    • Removed Text_skew specifications from the datasheet. This specifications are documented in the Intel® Stratix® 10 Configuration User Guide.
  • Updated the Configuration Bit Stream Sizes for Intel® Stratix® 10 Devices table.
    • Removed the IOCSR Bit Stream Size (Mbits) specifications.
    • Removed unsupported Intel® Stratix® 10 devices: MX 1100, GX 4500, GX 5500, SX 4500, and SX 5500.
    • Added Intel® Stratix® 10 devices: TX 850, TX 1100, GX 1660, and GX 2110.
    • Updated the Compressed Configuration Bit Stream Size specifications.
    • Added note on quad SPI flash.
  • Updated the Maximum Configuration Time Estimation tables.
    • Removed non-critical JTAG configuration mode specifications.
    • Removed unsupported configuration mode: AS ×1
    • Removed unsupported Intel® Stratix® 10 devices: MX 1100, GX 4500, GX 5500, SX 4500, and SX 5500.
    • Added Intel® Stratix® 10 devices: TX 850, TX 1100, GX 1660, and GX 2110.
  • Updated the Programmable IOE Delay for Intel® Stratix® 10 Devices table.
    • Corrected the speed grade to –E1V.
    • Updated the specifications for Fast Model and Slow Model.
  • Updated definition for VIX(AC) in the Glossary.
  • Added description to the following tables to state that the data in the table is preliminary.
    • H-Tile Transmitter Specifications
    • General Configuration Timing Specifications for Intel® Stratix® 10 Devices
    • Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices ( Avalon® -ST)
    • Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices (AS and SD/MMC)
2019.02.25
  • Changed the variants datasheet status from Preliminary to Final in the Datasheet Status for Intel® Stratix® 10 Devices table.
2019.02.05
  • Updated the maximum specifications for VI (for 3 V I/O) from 3.6 V to 3.8 V.
  • Added the LVPECL DC electrical characteristics table for the E-Tile transceiver reference clock.
  • Added the electrical and jitter requirements table for the E-Tile transceiver reference clock.
  • Merged the minimum, typical and maximum specifications for the E-Tile transmitter common mode voltage into one specification.
  • Updated the NRZ data rate for the E-Tile transceivers.
  • Added the performance specifications for the HBM2 interface in the Intel® Stratix® 10 MX devices.
  • Updated the temperature specifications for the HBM2 interface in Intel® Stratix® 10 devices.
  • Updated the Intel® Quartus® Prime Assignment Names in the Programmable IOE Delay for Intel® Stratix® 10 Devices table.
2018.10.25
  • Updated the description for the X suffix.
  • Removed the description on VREFP_ADC and VREFN_ADC I/O pins in the Maximum Allowed Overshoot During Transitions for Intel® Stratix® 10 Devices (for LVDS I/O) table.
  • Updated the Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
    • Updated the VCC and VCCP specifications for –3X speed grade.
    • Removed Pulse-Width Modulation (PWM) from the note to VCC and VCCP for SmartVID devices.
    • Updated the note to VCCBAT.
    • Removed the VREFP_ADC specifications.
  • Changed the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Non-Bonded Configuration" table.
  • Changed the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L-Tile Devices in a Bonded Configuration" table.
  • Changed the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX H-Tile Devices in a Bonded Configuration" table.
  • Changed the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX H-Tile Devices in a Bonded Configuration" table.
  • Updated the footnote specifying pll_powerdown minimum assertion cycles in the "Transceiver Performance for Intel Stratix 10 GX/SX L-Tile Devices" section.
  • Added a noise mask specification column and updated the symbol names in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 TX/MX E-Tile Devices" table.
  • Added a note about TX jitter specifications for the SerialLite III protocol in the "Transceiver Performance for Intel Stratix 10 GX/SX L-Tile Devices" section.
  • Removed the Transmitter REFCLK Phase Jitter (100 MHz) specification from the "L-Tile Reference Clock Specifications" table.
  • Added a note about PCI Express reference clock phase jitter specifications to the "Transceiver Specifications for Intel® Stratix® 10 GX/SX L-Tile Devices" section
  • Changed the GXT channel specification for chip-to-chip, -3 speed grade devices in the " Intel® Stratix® 10 GX/SX H-Tile Transmitter and Receiver Datarate Performance" table.
  • Added a note about TX jitter specifications for the SerialLite III protocol in the "Transceiver Performance for Intel Stratix 10 GX/SX H-Tile Devices" section.
  • Removed the Transmitter REFCLK Phase Jitter (100 MHz) specification from the "H-Tile Reference Clock Specifications" table.
  • Added a note about PCI Express reference clock phase jitter specifications to the "Transceiver Specifications for Intel® Stratix® 10 GX/SX H-Tile Devices" section
  • Removed PWM from the note to VCCL_HPS and VCCPLLDIG_HPS for SmartVID devices in the HPS Power Supply Operating Conditions for Intel® Stratix® 10 Devices table.
  • Updated the I/O PLL Specifications for Intel® Stratix® 10 Devices table.
    • Updated the maximum fVCO specifications for –3 speed grade.
    • Updated the description for tCASC_OUTPJ_DC.
  • Added series resistance and diode ideality factor parameters for E-Tile TSD in the External Temperature Sensing Diode Specifications for Intel® Stratix® 10 Devices table.
  • Added a note on half rate support for DDR3 SDRAM in the Memory Standards Supported by the Hard Memory Controller for Intel® Stratix® 10 Devices table.
  • Updated the Memory Standards Supported by the Soft Memory Controller for Intel® Stratix® 10 Devices table.
    • Added a note to RLDRAM 3
    • Updated QDR IV SRAM specification
    • Added a note on full rate support for QDR II SRAM
  • Removed the DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Intel® Stratix® 10 Devices table.
  • Updated the description in the Memory Output Clock Jitter Specifications section.
  • Updated the Maximum HPS Clock Frequencies for Intel® Stratix® 10 Devices table.
    • Updated the MPU frequency for VCCL_HPS = 0.94 V.
    • Added note to L3 Interconnect Frequency for VCCL_HPS = 0.94 V for –E1V, –I1V, –E2L, –I2L, –E3X, and –I3X.
  • Updated the specifications in the HPS Internal Oscillator Frequency for Intel® Stratix® 10 Devices table.
  • Updated the specifications for Tspi_ref_clk, Tdssfrst, and Tdsslst in the SPI Master Timing Requirements for Intel® Stratix® 10 Devices table.
  • Updated the specifications for Tspi_ref_clk and Th in the SPI Slave Timing Requirements for Intel® Stratix® 10 Devices table.
  • Updated the HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel® Stratix® 10 Devices table.
    • Updated the description for Tsdmmc_clk.
    • Removed the note to the minimum and maximum specifications for Td.
    • Updated the reference clock in the note for Td and Tsu.
  • Updated Tclk specifications in the following tables:
    • Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Intel® Stratix® 10 Devices
    • RGMII RX Timing Requirements for Intel® Stratix® 10 Devices
    • Reduced Media Independent Interface (RMII) Clock Timing Requirements for Intel® Stratix® 10 Devices
    • Management Data Input/Output (MDIO) Timing Requirements for Intel® Stratix® 10 Devices
  • Updated Td specification in the Management Data Input/Output (MDIO) Timing Requirements for Intel® Stratix® 10 Devices table.
  • Updated the title for the following diagrams:
    • RGMII TX and RMII TX Timing Diagram
    • RGMII RX and RMII RX Timing Diagram
  • Removed tCF02ST0 specifications for Device Security Feature (Zeroization) ON in the General Configuration Timing Specifications for Intel® Stratix® 10 Devices table.
  • Updated tJCP specification in the JTAG Timing Parameters and Values for Intel® Stratix® 10 Devices table.
  • Added Text_skew specifications in the AS Timing Parameters for Intel® Stratix® 10 Devices table.
  • Updated the Avalon-ST Configuration Timing Diagram.
  • Mentioned that the SD/MMC configuration scheme will be available in a future release of the Intel® Quartus® Prime software.SD/MMC Timing Parameters for Intel® Stratix® 10 Devices table.
  • Updated the Maximum Configuration Time Estimation section.
    • Clarify the maximum configuration time.
    • Updated the note to AVST ×8, AVST ×16, and AVST ×32.
  • Removed Preliminary tags for all table. Refer to the Data Status for Intel® Stratix® 10 Devices table for the data status for each variant.
2018.07.13 Corrected the typical values for VCC and VCCP in the Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
2018.07.12 Made the following changes:
  • Updated the Absolute Maximum Ratings for Intel® Stratix® 10 Devices table.
    • Updated the maximum values for VCCIO (for LVDS I/O), VCCIO_HPS, and VCCIO_SDM from 2.46 V to 2.19 V.
    • Updated the maximum value for VI (for LVDS I/O) from 2.5 V to 2.19 V.
    • Updated the IOUT specifications.
  • Updated the Maximum Allowed Overshoot and Undershoot Voltage section.
    • Updated the overshoot and undershoot values in the description.
    • Updated the specifications in the Maximum Allowed Overshoot During Transitions for Intel® Stratix® 10 Devices (for LVDS I/O) and Maximum Allowed Overshoot During Transitions for Intel® Stratix® 10 Devices (for LVDS I/O) tables.
    • Updated the voltages in the Intel® Stratix® 10 Devices Overshoot Duration diagram.
  • Added a footnote to 1.03 V typical voltage in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L-Tile Devices in a Non-Bonded Configuration" table.
  • Added a footnote to 1.03 V typical voltage in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L-Tile Devices in a Bonded Configuration" table.
  • Added a footnote to 1.03 V typical voltage in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Non-Bonded Configuration" table.
  • Added a footnote to 1.03 V typical voltage in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Bonded Configuration" table.
  • Changed the minimum and maximum voltage for VCCT_GXB and VCCR_GXB in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L-Tile Devices in a Non-Bonded Configuration" table.
  • Changed the minimum and maximum voltage for VCCT_GXB and VCCR_GXB in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L-Tile Devices in a Bonded Configuration" table.
  • Changed the minimum and maximum voltage for VCCT_GXB and VCCR_GXB in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX H-Tile Devices in a Non-Bonded Configuration" table.
  • Changed the minimum and maximum voltage for VCCT_GXB and VCCR_GXB in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX H-Tile Devices in a Bonded Configuration" table.
  • Updated VCC, VCCP, VCCBAT, VCCIO, VCCM_WORD, and VI specifications in the Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
  • Updated VCCL_HPS and VCCPLLDIG_HPS specifications in the HPS Power Supply Operating Conditions for Intel® Stratix® 10 Devices table.
  • Updated the OCT Without Calibration Resistance Tolerance Specifications for Intel® Stratix® 10 Devices table.
  • Removed Equation for OCT Variation Without Recalibration.
  • Added pin capacitance specifications.
  • Added the resistance tolerance for RPU in the Internal Weak Pull-Up Resistor Values for Intel® Stratix® 10 Devices table.
  • Updated the VCCIO specifications for POD12 in the Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel® Stratix® 10 Devices table.
  • Removed the VOL and VOH specifications for POD12 in the Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel® Stratix® 10 Devices table.
  • Updated VSWING(DC) specification for SSTL-12 in the Differential SSTL I/O Standards Specifications for Intel® Stratix® 10 Devices table.
  • Corrected VX(AC) to VIX(AC) in the Differential SSTL I/O Standards Specifications for Intel® Stratix® 10 Devices and Glossary tables.
  • Updated the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L-Tile Devices in a Non-Bonded Configuration" table.
  • Updated the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L-Tile Devices in a Bonded Configuration" table.
  • Updated the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Non-Bonded Configuration" table.
  • Updated the minimum and maximum values for VCCH_GXB[L,R] in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Bonded Configuration" table.
  • Changed the minimum, typical, and maximum values for VCCT_GXB[L,R] and VCCR_GXB[L,R] for datarates > 17.4 Gbps to 28.3 Gbps in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Bonded Configuration" table.
  • Changed the footnote for the minimum value of the Input Reference Clock Frequency (fPLL PLL) symbol in the "L-Tile Reference Clock Specifications" table.
  • Changed the minimum and maximum frequencies and added a Modes column to the "L-Tile Fractional PLL Performance" table.
  • Changed the minimum and maximum frequencies and added a Modes column to the "H-Tile Fractional PLL Performance" table.
  • Changed the minimum supported output frequency in the "L-Tile CMU PLL Performance" table.
  • Added a footnote to the Transmitter REFCLK Phase Jitter (100 MHz) specification in the "L-Tile Reference Clock Specifications" table.
  • Added a footnote to the Transmitter REFCLK Phase Noise (800 MHz) specification in the "H-Tile Reference Clock Specifications" table.
  • Removed the DC coupling description from the VICM symbol in the "L-Tile Receiver Specifications" table.
  • Added a footnote to the VOD Setting column in the "L-Tile Typical Transmitter VOD Settings" table.
  • Added a footnote to the GXT channels for transceiver speed grade -1 in the " Intel® Stratix® 10 GX/SX H-Tile Transmitter and Receiver Datarate Performance" table.
  • Changed the footnote for the minimum value of the Input Reference Clock Frequency (fPLL PLL) symbol in the "H-Tile Reference Clock Specifications" table.
  • Changed the maximum voltage for the VID (before device configuration) parameter in the "H-Tile Receiver Specifications" table.
  • Removed DC coupling support from the VICM parameter in the "H-Tile Receiver Specifications" table.
  • Added a footnote to the VOD Setting column in the "H-Tile Typical Transmitter VOD Settings" table.
  • Changed the VICM (AC Coupled) typical value in the "H-Tile Reference Clock Specifications" table.
  • Updated the programmable clock routing specification for –1 speed grade in the Clock Tree Performance for Intel® Stratix® 10 Devices table.
  • Updated the Fractional PLL Specifications for Intel® Stratix® 10 Devices table.
    • Updated fVCO specifications.
    • Removed tPLL_PSERR specifications.
  • Updated the Memory Block Performance Specifications for Intel® Stratix® 10 Devices table.
    • Added the specifications for the "Simple dual-port with ECC and optional pipeline registers enabled, with the read-during-write option set to Old Data, 512 × 32" mode in the M20K block.
    • Updated the specifications for eSRAM.
  • Updated specifications in the External Temperature Sensing Diode Specifications for Intel® Stratix® 10 Devices table.
  • Updated the Internal Voltage Sensor Specifications for Intel® Stratix® 10 Devices table.
  • Removed the note on pending silicon characterization in the High-Speed I/O Specifications for Intel® Stratix® 10 Devices table.
  • Added the following tables:
    • Memory Standards Supported by the Hard Memory Controller for Intel® Stratix® 10 Devices
    • Memory Standards Supported by the Soft Memory Controller for Intel® Stratix® 10 Devices
    • Memory Standards Supported by the HPS Hard Memory Controller for Intel® Stratix® 10 Devices
  • Removed the note to the DLL reference clock input specification in the DLL Frequency Range Specifications for Intel® Stratix® 10 Devices table.
  • Removed the Memory Output Clock Jitter Specifications for Intel® Stratix® 10 Devices table. Stated that the clock jitter is within the JEDEC specifications.
  • Updated TRS_RT specification in the OCT Calibration Block Specifications for Intel® Stratix® 10 Devices table.
  • Updated the note to SDRAM interconnect frequency in the Maximum HPS Clock Frequencies for Intel® Stratix® 10 Devices table.
  • Added HPS Internal Oscillator Frequency specifications.
  • Updated the minimum specification for clock input accuracy in the HPS PLL Input Requirements for Intel® Stratix® 10 Devices table.
  • Updated the minimum specifications for Td, Tsu, and Th in the HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel® Stratix® 10 Devices table.
  • Updated specifications in the HPS Programmable I/O Delay for Intel® Stratix® 10 Device table.
  • Removed Preliminary tags for the following tables:
    • HPS PLL Input Requirements for Intel® Stratix® 10 Devices
    • HPS PLL Performance for Intel® Stratix® 10 Devices
    • HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel® Stratix® 10 Devices
    • HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel® Stratix® 10 Devices
    • HPS I2C Timing Requirements for Intel® Stratix® 10 Devices
    • HPS NAND ONFI 1.0 Timing Requirements for Intel® Stratix® 10 Devices
    • HPS GPIO Interface
    • HPS JTAG Timing Requirements for Intel® Stratix® 10 Devices
    • HPS Programmable I/O Delay for Intel® Stratix® 10 Device
  • Removed information on NAND configuration mode.
    • Removed NAND mode in the POR Delay Specification for Intel® Stratix® 10 Devices table.
    • Removed the NAND Configuration Timing section.
    • Removed the maximum configuration time estimation for NAND mode.
  • Updated the note to clock input frequency in the External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements table.
  • Added description in the SD/MMC Timing Parameters for Intel® Stratix® 10 Devices table.
  • Removed the statement stating that the maximum configuration time does not exceed 2× of the minimum configuration time in the Maximum Configuration Time Estimation section.
  • Updated the I/O Timing section on the I/O timing information generation guidelines.
  • Updated the specifications for fast and slow models in the Programmable IOE Delay for Intel® Stratix® 10 Devices table.
  • Finalized the data for the Intel® Stratix® 10 GX variant (L-Tile).
  • Changed the input reference clock frequency (CMU PLL) minimum specification in the "L-Tile Reference Clock Specifications" table.
  • Changed the input reference clock frequency (CMU PLL) minimum specification in the "H-Tile Reference Clock Specifications" table.
2018.04.06 Made the following changes:
  • Added notes to IOUT specification in the Absolute Maximum Ratings for Intel® Stratix® 10 Devices table.
  • Updated the AS Timing Parameters for Intel® Stratix® 10 Devices table.
    • Updated the specifications for Tclk, Tdcsfrs, Tdcslst, and Tdo.
    • Removed the Text_skew specifications.
    • Updated the description on trace length matching and skew tolerance.
    • Updated the note for Text_delay.
  • Removed footnote to sampling rate in the Internal Voltage Sensor Specifications for Intel® Stratix® 10 Devices table.
  • Updated the specifications for tSDCLKP, tSU, and tH in the SD/MMC Timing Parameters for Intel® Stratix® 10 Devices table.
  • Updated the compressed configuration bit stream sizes in the Configuration Bit Stream Sizes table.
  • Updated the Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices tables.
    • Changed the table title from "Minimum Configuration Time Estimation" to "Maximum Configuration Time Estimation".
    • Updated the specifications.
2017.12.15 Made the following changes:
  • Added the Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L-Tile Devices in a Non-Bonded Configuration table.
  • Added the Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L-Tile Devices in a Bonded Configuration table.
  • Added the Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Non-Bonded Configuration table.
  • Added the Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 H-Tile Devices in a Bonded Configuration table.
  • Removed the Transceiver Power Supply Operating Conditions for Intel Stratix 10 GX/SX L- and H-Tile Devices table.
  • Removed the L-Tile Transmitter and Receiver Data Rate Performance, VCCR_GXB and VCCT_GXB Specifications table.
  • Added the Intel® Stratix® 10 GX/SX L-Tile Transmitter and Receiver Datarate Performance table.
  • Added the Intel® Stratix® 10 GX/SX H-Tile Transmitter and Receiver Datarate Performance table.
  • Removed the H-Tile Transmitter and Receiver Data Rate Performance, VCCR_GXB and VCCT_GXB Specifications table
  • Added note to the Maximum" column in the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX L- and H-Tile Devices—Preliminary table.
  • Removed the Minimum differential eye opening at receiver serial input pins specification from the "L-Tile Receiver Specifications" table.
  • Updated Absolute Maximum Ratings for Intel® Stratix® 10 Devices table.
    • Updated TSTG minimum specifications from –65°C to –55°C.
    • Added VI specifications.
  • Added -2 transceiver speed grade,the tARESET, and the tLOCK specification to the "L-Tile ATX PLL Performance" table.
  • Added the tARESET and tLOCK specifications to the "L-Tile Fractional PLL Performance" table.
  • Added the tARESET and tLOCK specifications to the "L-Tile CMU PLL Performance" table.
  • Changed the Channel Span definition in the "L-Tile Transceiver Clock Network Maximum Data Rate Specifications" table.
  • Removed the VOCM (DC coupled) specification from the "L-Tile Transmitter Specifications" table.
  • Added the xN clock mode to the "L-Tile Transmitter Channel-to-channel Skew Specifications" table.
  • Added the xN clock mode to the "H-Tile Transmitter Channel-to-channel Skew Specifications" table.
  • Added the tLOCK and tARESET specifications to the "H-Tile ATX PLL Performance" table.
  • Added the tLOCK and tARESET specifications to the "H-Tile Fractional PLL Performance" table.
  • Added the tLOCK and tARESET specifications to the "H-Tile CMU PLL Performance" table.
  • Removed the Minimum differential eye opening at receiver serial input pins specification from the "H-Tile Receiver Specifications" table.
  • Split LVDS I/O and 3 V I/O specifications in Maximum Allowed Overshoot During Transitions for Intel® Stratix® 10 Devices table into two separate tables. Updated the LVDS I/O specifications.
  • Added Intel® Stratix® 10 Devices Overshoot Duration figure and description.
  • Updated Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
    • Updated VCCIO_UIB specifications.
    • Updated note to minimum and maximum columns.
    • Changed the symbol from VCCM to VCCM_WORD.
  • Added specifications for VCCIO = 2.5 V in the following tables:
    • Bus Hold Parameters for Intel® Stratix® 10 Devices
    • Internal Weak Pull-Up Resistor Values for Intel® Stratix® 10 Devices
  • Updated specifications in OCT Calibration Accuracy Specifications for Intel® Stratix® 10 Devices table.
  • Updated specifications in OCT Without Calibration Resistance Tolerance Specifications for Intel® Stratix® 10 Devices table.
    • Added specifications for VCCIO = 3.0, 2.5
    • Updated specifications for VCCIO = 1.8, 1.5, 1.2
  • Added the following specifications in Single-Ended I/O Standards Specifications for Intel® Stratix® 10 Devices table.
    • 2.5 V I/O standard
    • Schmitt trigger input
  • Updated SSTL-125 and SSTL-135 I/O standards in Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel® Stratix® 10 Devices table.
  • Added specifications for SSTL-12 I/O standard in the following tables:
    • Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel® Stratix® 10 Devices
    • Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel® Stratix® 10 Devices
    • Differential SSTL I/O Standards Specifications for Intel® Stratix® 10 Devices
  • Updated the Fractional PLL Specifications for Intel® Stratix® 10 Devices table.
    • Updated tPLL_PSERR specifications.
    • Updated tLOCK description.
    • Removed tARESET specifications.
  • Updated tOUTDUTY in the I/O PLL Specifications for Intel® Stratix® 10 Devices table.
  • Updated Internal Temperature Sensing Diode Specifications for Intel® Stratix® 10 Devices table.
    • Added note for temperature range.
    • Updated conversion time from < 5 ms to < 1 ms.
    • Removed "Resolution" and "Minimum Resolution with no Missing Codes" specifications.
  • Updated High-Speed I/O Specifications for Intel® Stratix® 10 Devices table.
    • Updated Transmitter—TCCS specifications from 150 ps to 330 ps.
    • Updated Sampling Window specifications from 300 ps to 330 ps.
    • Updated SERDES factor J = 3 maximum data rate for transmitter and receiver.
  • Updated from 0.35 to 0.28 for the following:
    • LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps
    • LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps
  • Updated DLL reference clock input specifications in DLL Frequency Range Specifications for Intel® Stratix® 10 Devices table.
  • Updated Tdo minimum specification from 0 ns to –1 ns in AS Timing Parameters for Intel® Stratix® 10 Devices table.
  • Updated minimum specifications for tH from 0 ns to –1 ns in SD/MMC Timing Parameters for Intel® Stratix® 10 Devices table.
  • Updated Configuration Bit Stream Sizes for Intel® Stratix® 10 Devices table.
    • Added IOCSR bit stream sizes.
    • Added specifications for Intel® Stratix® 10 TX and MX devices.
  • Updated Minimum Configuration Time Estimation for Intel® Stratix® 10 Devices tables.
    • Added note to AVST ×8, AVST ×16, and AVST ×32.
    • Updated specifications for NAND.
    • Added specifications for Intel® Stratix® 10 TX and MX devices.
  • Added the following tables:
    • External Temperature Sensing Diode Specifications for Intel® Stratix® 10 Devices
    • General Configuration Timing Specifications for Intel® Stratix® 10 Devices
      • Moved tST0 specifications from Avalon-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel® Stratix® 10 Devices table.
      • Moved the specifications from Initialization Time for Intel® Stratix® 10 Devices table.
    • Programmable IOE Delay for Intel® Stratix® 10 Devices
2017.08.04 Made the following changes:
  • Clarified DLL operating frequency range in "DLL Range Specifications"
  • Clarified reference clock specifications in "HPS SPI Timing Characteristics"
2017.05.08 Made the following changes:
  • Updated description for VCCERAM in Absolute Maximum Ratings for Intel® Stratix® 10 Devices table.
  • Added Maximum Allowed Overshoot During Transitions for Intel® Stratix® 10 Devices table.
  • Updated Recommended Operating Conditions for Intel® Stratix® 10 Devices table.
    • Updated VCC, VCCIO, and VCCBAT specifications.
    • Updated symbol from VCCPFUSE_SDM to VCCFUSEWR_SDM.
    • Updated description for VCCERAM and VCCIO_UIB .
    • Added VCCM specifications.
    • Added footnotes to tRAMP and V suffix speed grades.
  • Removed table: Temperature Compensation for SmartVID for Intel® Stratix® 10 Devices. Moved the table to the Intel® Stratix® 10 Power Management User Guide.
  • Updated the note in the "Transceiver Power Supply Operating Conditions" section.
  • Updated HPS Power Supply Operating Conditions for Intel® Stratix® 10 Devices table.
    • Updated VCCL_HPS and VCCPLLDIG_HPS specifications.
    • Added footnote for SmartVID.
  • Updated footnote to IOL and IOH in Single-Ended I/O Standards Specifications for Intel® Stratix® 10 Devices table.
  • Updated Differential I/O Standards Specifications for Intel® Stratix® 10 Devices table.
    • Changed DMAX to data rate.
    • Added a note to VOD.
  • Updated tOUTPJ_DC and tOUTCCJ_DC specifications in I/O PLL Specifications for Intel® Stratix® 10 Devices.
  • Changed the units of measure for the minimum frequency in the "L-Tile CMU PLL Performance" table.
  • Changed the units of measure for the minimum frequency in the "H-Tile CMU PLL Performance" table.
  • Updated tINCCJ specification for FREF < 100 MHz in the following tables:
    • Fractional PLL Specifications for Intel® Stratix® 10 Devices
    • I/O PLL Specifications for Intel® Stratix® 10 Devices
  • Added footnote to the following modes in DSP Block Performance Specifications for Intel® Stratix® 10 Devices table:
    • Fixed-point 27 × 27 multiplication mode
    • Fixed-point 18 × 18 multiplier adder mode
    • Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode
  • Updated soft CDR mode specifications in High-Speed I/O Specifications for Intel® Stratix® 10 Devices table.
  • Added POR specifications.
  • Updated Tdo maximum specification in AS Timing Parameters for Intel® Stratix® 10 Devices table.
  • Updated notes in Avalon-ST Configuration Timing Diagram.
  • Added description in NAND ONFI 1.0 Mode 0-5 Timing Requirements for Intel® Stratix® 10 Devices table.
  • Updated tSU, tH, and td specifications in SD/MMC Timing Parameters for Intel® Stratix® 10 Devices table.
  • Updated table title from "Initialization Clock Source Option and the Maximum Frequency for Intel® Stratix® 10 Devices" to "Initialization Time for Intel® Stratix® 10 Devices".
  • Updated description in Configuration Bit Stream Sizes for Intel® Stratix® 10 Devices to mention that the actual sizes may be equal or smaller than the bit stream sizes in this table.
  • Updated description in Minimum Configuration Time Estimation section.
  • Removed AS ×1 specifications in Minimum Configuration Time Estimation for Intel® Stratix® 10 Devices (AS, NAND, and SD/MMC) table.
  • Added Glossary.
  • Removed PowerPlay text from tool name.
2017.02.17 Made the following changes:
  • Added the "Transceiver Power Supply Operating Conditions for Intel® Stratix® 10 GX/SX E-Tile Devices" table.
  • Added the "E-Tile Transceiver Performance Specifications" section.
  • Added the "Transceiver Performance for Intel® Stratix® 10 E-Tile Devices" section.
  • Added the "Transceiver Reference Clock Specifications" section.
  • Added the "Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices" section.
  • Added the "Receiver Specifications for Intel® Stratix® 10 E-Tile Devices" section.
  • Updated the "AS Timing Parameters for Intel® Stratix® 10 Devices" table.
    • Updated Tdcsfrs and Tdcslst.
    • Added Text_delay and Text_skew.
    • Removed Tsu and Th.
  • Updated AS Configuration Serial Input Timing Diagram.
2016.12.09 Made the following changes:
  • Changed the max tLTR value and unit of measure in the "L-Tile Receiver Specifications" table.
  • Made the following changes to the "Transceiver Clocks Specifications for Stratix 10 GX/SX L-Tile Devices" table:
    • Changed the value of the reconfig_clk signal
    • Added a new footnote to the GX channel
    • Changed the minimum values for the GXT channel
  • Changed the max tLTR value and unit of measure in the "H-Tile Receiver Specifications" table.
  • Removed the QPI footnote from the "H-Tile Transmitter Specifications" table.
  • Changed the value of the reconfig_clk signal in the "Transceiver Clocks Specifications for Stratix 10 GX/SX H-Tile Devices" table.
  • Changed the minimum value of fINPFD in the "Fractional PLL Specifications for Stratix 10 Devices" table.
2016.10.31 Initial release.
Level Two Title