Visible to Intel only — GUID: mcn1441702755056
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
Memory Standards Supported by the Soft Memory Controller
Memory Standards Supported by the HPS Hard Memory Controller
DLL Range Specifications
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices
HBM2 Interface Performance
OCT Calibration Block Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: mcn1441702755056
Ixiasoft
Differential I/O Standards Specifications
I/O Standard | VCCIO (V) | VID (mV) 38 | VICM(DC) (V) | VOD (V) 39 40 | VOCM (V) 39 | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
LVDS 41 | 1.71 | 1.8 | 1.89 | 100 | — | 0.05 | Data rate ≤700 Mbps | 1.65 | 0.247 | — | 0.6 | 1.125 | 1.25 | 1.375 |
1 | Data rate >700 Mbps | 1.6 | ||||||||||||
RSDS41 | 1.71 | 1.8 | 1.89 | 100 | — | 0.3 | — | 1.4 | 0.1 | 0.2 | 0.6 | 0.5 | 1.2 | 1.4 |
Mini-LVDS 42 | 1.71 | 1.8 | 1.89 | 200 | 600 | 0.4 | — | 1.325 | 0.25 | — | 0.6 | 1 | 1.2 | 1.4 |
LVPECL41 | 1.71 | 1.8 | 1.89 | 300 | — | 0.6 | Data rate ≤700 Mbps | 1.7 | — | — | — | — | — | — |
1 | Data rate >700 Mbps | 1.6 |
38 The minimum VID value is applicable over the entire common mode range, VCM.
39 RL range: 90 ≤ RL ≤ 110 Ω.
40 The specification is only applicable to default VOD setting. Intel recommends performing IBIS or HSPICE simulation to estimate the buffer's electrical performance when non-default VOD setting is used.
41 For optimized receiver performance, the receiver voltage input must be within the Vicm min and Vicm max limit specified in the table and at the same time adhering to the minimum and maximum absolute ratings specification. Refer to Absolute Maximum Ratings for Intel Stratix 10 Devices table for the range of the minimum and maximum absolute ratings for the DC input voltage for LVDS I/O.
42 For optimized Mini-LVDS receiver performance, the receiver voltage input must be within the minimum voltage of VICM(Min) - VID(Max)/2 and the maximum voltage of VICM(Max) + VID(Max)/2.