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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
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1.6.1.7. Transport Layer
The transport layer in the JESD204B IP core consists of an assembler at the TX path and a deassembler at the RX path.
The transport layer provides the following services to the application layer (AL) and the DLL:
- The assembler at the TX path:
- maps the conversion samples from the AL (through the Avalon® streaming interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
- reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during TX data streaming.
- The deassembler at the RX path:
- maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon® streaming interface).
- reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during RX data streaming.