JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

ID 683094
Date 7/19/2024
Public
Document Table of Contents

1.6.1.7. Transport Layer

The transport layer in the JESD204B IP core consists of an assembler at the TX path and a deassembler at the RX path.

The transport layer provides the following services to the application layer (AL) and the DLL:

  • The assembler at the TX path:
    • maps the conversion samples from the AL (through the Avalon® streaming interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
    • reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during TX data streaming.
  • The deassembler at the RX path:
    • maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon® streaming interface).
    • reports AL error to the DLL if it encounters a specific error condition on the Avalon® streaming interface during RX data streaming.