Visible to Intel only — GUID: bhc1411116986894
Ixiasoft
Visible to Intel only — GUID: bhc1411116986894
Ixiasoft
1.6.1.4. Transceiver Reset Controller
The transceiver reset controller uses the Altera's Transceiver PHY Reset Controller IP Core to ensure a reliable initialization of the transceiver. The reset controller has separate reset controls per channel to handle synchronization of reset inputs, hysteresis of PLL locked status, and automatic or manual reset recovery mode.
In this design example, the reset controller targets both the TX and RX channels. The TX PLL , TX Channel , and RX Channel parameters are programmable to accommodate single and multiple (2) JESD204B links.