JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

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ID 683094
Date 7/19/2024
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1. JESD204B Intel® FPGA IP Design Example User Guide

1.2. Supported Configurations

The design examples only support a limited set of JESD204B IP core parameter configurations.
The IP Catalog parameter editor allows you to generate a design example only if the parameter configurations matches those in the tables below.
Table 3.  Supported JESD204B IP Core Parameter Configurations (L, M, F Values)
JESD204B IP Parameters Applicable Devices
L M F
1 1 2 V series and Arria® 10
1 1 4 V series and Arria® 10
1 1 8 Arria® 10
1 2 4 V series and Arria® 10
1 2 8 Arria® 10
1 4 8 V series and Arria® 10
2 1 1 V series and Arria® 10
2 1 2 V series and Arria® 10
2 1 4 V series and Arria® 10
2 1 8 Arria® 10
2 2 2 V series and Arria® 10
2 2 4 V series and Arria® 10
2 2 8 Arria® 10
2 4 4 V series and Arria® 10
2 4 8 Arria® 10
2 8 8 Arria® 10
4 1 1 Arria® 10
4 1 2 Arria® 10
4 2 1 V series and Arria® 10
4 2 2 V series and Arria® 10
4 2 4 Arria® 10
4 2 8 Arria® 10
4 4 2 V series and Arria® 10
4 4 4 V series and Arria® 10
4 4 8 Arria® 10
4 8 4 V series and Arria® 10
4 8 8 Arria® 10
4 16 8 Arria® 10
6 1 1 Arria® 10
6 3 1 Arria® 10
8 1 1 V series and Arria® 10
8 1 2 Arria® 10
8 2 1 V series and Arria® 10
8 2 2 Arria® 10
8 2 4 Arria® 10
8 4 1 V series and Arria® 10
8 4 2 V series and Arria® 10
8 4 4 Arria® 10
8 4 8 Arria® 10
8 8 2 Arria® 10
8 8 4 Arria® 10
8 8 8 Arria® 10
8 16 4 Arria® 10
8 16 8 Arria® 10
8 32 8 Arria® 10
Table 4.  Supported JESD204B IP Core Parameter Configurations
JESD204B IP Parameters Value
Wrapper Options Both Base and Phy
Data Path Duplex
JESD204B Subclass 1
Data Rate
  • 6144 (Arria V, Stratix V, and Arria 10)
  • 5000 (Cyclone V)
PCS Option Enabled Hard PCS
PLL Type CMU2
Bonding Mode
  • Bonded (For Enable Transceiver Dynamic Reconfiguration option set to No)
  • Non-bonded (For Enable Transceiver Dynamic Reconfiguration option set to Yes)
Enable Transceiver Dynamic Reconfiguration
  • No (Bonding Mode must be set to Bonded)
  • Yes (Bonding Mode must be set to Non-bonded)
  • For Arria 10:
    • No (only the RTL state machine control design example is available for generation)
PLL/CDR Reference Clock Frequency
  • 153.6 (Arria V, Stratix V, and Arria 10; all supported L parameter values except L=8)
  • 307.2 (Arria V, Stratix V, and Arria 10; L=8)
  • 125 (Cyclone V; all supported L parameter values except L=8)
  • 250 (Cyclone V; L=8)
Enable Bit Reversal And Byte Reversal No
N
  • 16 (V series)
  • 12, 13, 14, 15, 16 ( Arria® 10)
N’ 16
CS
  • 0 (V series)
  • 0-3 ( Arria® 10)
CF 0
High Density User Data Format (HD)
  • 0 (V series)
  • 0 for F = 2, 4, 8 ( Arria® 10)
  • 1 for F = 1 ( Arria® 10)
Enable scramble (SCR) Yes
Enable Error Code Correction (ECC_EN) Yes
Table 5.  Valid Options Available for Design Example Generation
Device Supported JESD204B IP Core Configurations Example Design Type Generate Generic Example Design? Example Design Files HDL Format Target Development Kit

Stratix V, Arria V, Cyclone V

 No None No — — —
No None Generic RTL Simulation Verilog, VHDL —
No None Generic RTL Synthesis Verilog 3 —
Yes RTL — Simulation Verilog, VHDL —
Yes RTL — Synthesis Verilog 3 —
Arria 10 No None No — — —
No None Generic RTL Simulation Verilog, VHDL —
No None Generic RTL Synthesis Verilog 3 —
Yes RTL — Simulation Verilog, VHDL —
Yes RTL — Synthesis Verilog 3 —
2 Not applicable to Arria 10 devices.
3 For synthesis flow, only the Verilog HDL format is available.
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