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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
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1.1.3.1. Procedure
To compile and simulate the design:
- Change the working directory to <example_design_directory>/ed_sim/
- Type one of the following to generate the simulation files:
- For verilog: quartus_sh -t gen_ed_sim_verilog.tcl
- For vhdl: quartus_sh -t gen_ed_sim_vhdl.tcl
- Change the working directory to <example_design_directory>/ed_sim/testbench/<Simulator>.
- Run the simulation script for the simulator of your choice. Refer to the table below.
Simulator Command ModelSim* do run_tb_top.tcl VCS* / VCS* MX sh run_tb_top.sh Aldec do run_tb_top.tcl Xcelium* sh run_tb_top.sh A successful simulation ends with the following message, "Simulation stopped due to successful completion! Simulation passed."