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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
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1.6.1.5.1. Parallel PRBS Generator
PRBS generator circuits often consists of simple shift registers with feedback that serve as test sources for serial data links. The output sequence is not truly random but repeats after 2X–1 bits, where X denotes the length of the shift register. Polynomial notation—which the polynomial order corresponds to the length of the shift register and the period of PRBS—provides a method of describing the sequence.