JESD204B Intel® FPGA IP Design Example User Guide: Quartus® Prime Standard Edition

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ID 683094
Date 7/19/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP Design Example User Guide
1. JESD204B Intel® FPGA IP Design Example User Guide x
1.1. JESD204B Design Example Quick Start Guide 1.2. Supported Configurations 1.3. Generic Design Example 1.4. Presets 1.5. Selecting and Generating the Design Example 1.6. Design Example with RTL State Machine Control Unit 1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives 1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
1.1. JESD204B Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Compiling and Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Procedure 1.1.2.2. Design Example Parameters
1.1.3. Compiling and Simulating the Design x
1.1.3.1. Procedure
1.6. Design Example with RTL State Machine Control Unit x
1.6.1. Design Example Components 1.6.2. System Parameters 1.6.3. System Interface Signals 1.6.4. Example Feature: Dynamic Reconfiguration 1.6.5. Generating and Simulating the Design Example 1.6.6. Generating the Design Example For Compilation 1.6.7. Compiling the JESD204B IP Core Design Example
1.6.1. Design Example Components x
1.6.1.1. PLL 1.6.1.2. PLL Reconfiguration 1.6.1.3. Transceiver Reconfiguration Controller 1.6.1.4. Transceiver Reset Controller 1.6.1.5. Pattern Generator 1.6.1.6. Pattern Checker 1.6.1.7. Transport Layer 1.6.1.8. Serial Port Interface (SPI) 1.6.1.9. Control Unit
1.6.1.5. Pattern Generator x
1.6.1.5.1. Parallel PRBS Generator 1.6.1.5.2. Alternate Checkerboard Generator 1.6.1.5.3. Ramp Wave Generator
1.6.1.6. Pattern Checker x
1.6.1.6.1. Parallel PRBS Checker 1.6.1.6.2. Alternate Checkerboard Checker 1.6.1.6.3. Ramp Wave Checker
1.6.1.7. Transport Layer x
1.6.1.7.1. Supported System Configuration 1.6.1.7.2. Data Bit and Content Mapping Scheme 1.6.1.7.3. TX Path 1.6.1.7.4. RX Path
1.6.1.9. Control Unit x
1.6.1.9.1. Memory Block (ROM) 1.6.1.9.2. Finite State Machine (FSM)
1.6.2. System Parameters x
1.6.2.1. Run-Time Reconfiguration
1.6.4. Example Feature: Dynamic Reconfiguration x
1.6.4.1. Dynamic Reconfiguration Operation 1.6.4.2. MIF ROM
1.6.5. Generating and Simulating the Design Example x
1.6.5.1. Generating the Design Example Simulation Model 1.6.5.2. Simulating the JESD204B IP Core Design Example
1. JESD204B Intel® FPGA IP Design Example User Guide

1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version Changes
2024.07.19 24.2 Removed Nios® II support.
2022.10.31 22.1
  • Updated NCSim to Xcelium.
  • Updated the JESD204B Intel® FPGA IP Design Example User Guide Document Archives section.
  • Updated Qsys to Platform Designer (Standard).
Date Version Changes
November 2017 2017.11.06
  • Added note stating CMU PLL is not applicable to Arria 10 devices in Supported JESD204B IP Core Parameter Configurations and IP Parameter Settings for Generic Design Example.
  • Added note to System Clocking for the Design Example table about additional jitter introduced to the ATX, fPLL, and transmit PLL output when using reference clock from a cascaded PLL output, global clock or core clock network.
May 2017 2017.05.08
  • Rebranded to Intel.
  • Added note to state the design example caters is applicable for Quartus® Prime Standard Edition only.
October 2016 2016.10.31
  • Updated supported configuration.
  • Updated supported parameter values for static reconfiguration.
  • Added note stating that the Qsys does not allow multiple system with same name in Nios II Subsystem in Qsys.
  • Added steps in Compiling and Simulating Design.
  • Updated document title.
May 2016 2016.05.02 Initial release.
Level Two Title