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1.1. JESD204B Design Example Quick Start Guide
1.2. Supported Configurations
1.3. Generic Design Example
1.4. Presets
1.5. Selecting and Generating the Design Example
1.6. Design Example with RTL State Machine Control Unit
1.7. JESD204B Intel® FPGA IP Design Example User Guide Document Archives
1.8. Document Revision History for the JESD204B Intel® FPGA IP Design Example User Guide
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1.6.7. Compiling the JESD204B IP Core Design Example
You can use the generated .qip file to include relevant files into your project. Generate the Quartus® Prime synthesis compilation files by running the script (gen_quartus_synth.tcl) located in the <example_design_directory>/ed_synth/ directory.
Note: If you use the Tcl console in the Quartus® Prime software to generate the gen_quartus_synth.tcl script, close all Quartus® Prime project before you start generating.
To compile your design using the Quartus® Prime software , follow these steps:
- Launch the Quartus® Prime software.
- On the File menu, click Open Project > Select <example_design_directory>/ed_synth/example_design/.
- Select jesd204b_ed.qpf. 15
- On the Processing menu, click Start Compilation.
At the end of the compilation, the Quartus® Prime software provides a pass/fail indication.
15 This is the default quartus project file that the Quartus® Prime software automatically generates. You can edit this file and the .qsf file according to your design preference.