AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Scope of This Document

This document is an overview of the coordinated hardware and software workflows required for partial reconfiguration. A basic review of the PR feature from the perspectives of the FPGA logic designer and host software designer is provided. A simple design example is included, with steps to generate it. This basic example enables software developers to generate FPGA images for testing without requiring in-depth knowledge of FPGA design. The example also enables FPGA designers to test more complicated FPGA designs without expert level experience with Linux.

The PR design methodology and design flow have a significant number of guidelines and restrictions. This document does not provide a complete definition of the PR design flow. Enough information is provided to let you get started. Following steps in the document, you generate an example PR design based on the SoC GHRD. FPGA logic design considerations for PR that impact the host software developer are also covered.

This document describes how to create FPGA configuration images. Step by step instructions for modifying a basic design example are included.

The FPGA logic designer must provide certain information to the host software developer for PR management to work correctly and reliably with the HPS. Guidelines for this handoff are provided.

If you are an FPGA logic designer, Intel® encourages you to review the software steps as an introduction to enabling PR on the device. You should also review the Quartus Prime Pro Edition Handbook Volume 1: Design and Compilation and the Arria 10 GSRD v16.1 Getting Started Guide on RocketBoards.org for further information about PR restrictions, advanced features, and best practices to help you create more complicated and impactful designs.

This document provides an overview of the process used to manage reconfigurable regions using Linux running on the HPS. There are ways to manage the reconfigurable logic regions without involving the HPS host software, but this document does not cover those methods.

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