AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Overview of Software Image Creation

The SoC FPGA GSRD provided on rocketboards.org is not initially set up for PR. The Linux kernel is compiled with the required configuration options for PR, and the preferred command line tool for managing device tree overlays is provided, but the device tree loaded at boot (the “live tree”) is not laid out properly for PR.

The Linux kernel build configuration options required for PR are shown in the following list. These options must be set in the socfpga_defconfig file when rebuilding the Linux kernel as described on rocketboards.org. The Linux kernel provided with the GSRD was built with these options enabled. 

CONFIG_FPGA=y
CONFIG_FPGA_REGION=y
CONFIG_FPGA_MGR_SOCFPGA=y
CONFIG_FPGA_MGR_SOCFPGA_A10=y
CONFIG_FPGA_BRIDGE=y
CONFIG_SOCFPGA_FPGA_BRIDGE=y
CONFIG_ALTERA_FREEZE_BRIGE=y
CONFIG_OF=y
CONFIG_OF_OVERLAY=y
CONFIG_OF_CONFIGFS=y
CONFIG_CONFIGFS_FS=y

The command line tool used to manage device tree overlays is called dtbt, an open source Python script. The source code is provided at altera-opensource/dtbt on GitHub. The software tool is provided in the /sbin/ directory of the GSRD SD card image. Use dtbt -h for more information.

The default device tree provided with the GSRD is not set up for PR. To support PR, the device tree loaded at boot must contain a definition of the FPGA regions linking the HPS FPGA manager and the bridge controllers to the top level FPGA region. The default tree provided on the GSRD SD card image from rocketboards.org does not provide this linkage.

After a proper device tree is loaded at Linux boot time, the dtbt tool is used to load and unload device tree overlays to modify the live tree.

The instructions provided in this document describe how to build a minimal boot device tree to support PR. Instructions are also provided on how to build the required device tree overlays, where to place them within the Linux directory structure on the SD card, and how to load and unload them using the dtbt command line tool.

To create and run the software image, you carry out these steps:

  1. Rebuild the Linux kernel with build configuration options for PR
  2. Create a Linux device tree describing the FPGA manager and the bridge controllers in relation to the top-level configuration region
  3. Create device tree overlays for personas in each PR region
  4. Place the device trees in the correct location in the Linux directory structure
  5. Boot the Linux system, loading the default device tree and the base revision overlay
  6. Use the dtbt tool to load and unload device tree overlays for various personas
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