AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Creating the Partial Reconfiguration Design

This design contains all the logic for the default persona of the PR region that is added to the GHRD Qsys design later.

The PR region contains three components for this example:

  • An Avalon-MM pipeline bridge, to split the bus address space for the other two components and isolate bus timing.
  • Memory to access from the Avalon-MM bus.
  • A system ID peripheral component. This component is accessible from the Avalon-MM bus and provides a static version number that can be read by software to determine what logic has been loaded into the PR region.
To create the PR design, perform the following steps:
  1. Open the Qsys Pro tool again and create a new system design named pr_region_default.qsys.
    Figure 8. Creating the Qsys Project for the Partial Reconfiguration Design
  2. Add an Avalon-MM pipeline bridge to the design as shown below.
    Figure 9. Adding the Avalon-MM Pipeline Bridge
  3. Add a 512 byte, 32-bit wide on-chip memory as shown below.
    Note: Scroll down and turn off the Initialize Memory Content option. Otherwise, Qsys will require an initialization data file.
    Figure 10. Adding On-Chip Memory
  4. Add a system ID peripheral component as shown below. Set the 32-bit System ID field to something unique.
    Figure 11. Adding the System ID
  5. Hook up the Qsys system as shown below by clicking on the appropriate connection bubbles.
    Figure 12. Configuring the System Connections
  6. Export the Avalon-MM pipeline bridge slave port and give it an exported name of s0.
  7. Change the on-chip base address to 0x0200 and leave the system ID peripheral base address at 0x0000.
  8. Confirm the address map is correct by reviewing the configuration in the Address Map tab. It should look like the configuration shown below.
    Figure 13. Address Map Example
  9. Save the design and click Finish.
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