AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Important Partial Reconfiguration Terminology

Implementing a partial reconfiguration (PR) design requires understanding of the FPGA device capabilities and the Quartus Prime Pro compilation flow. This section defines common terminology that you need to fully understand PR.

Core logic: Logic resources on the device which have no direct off-chip connections, such as LABs, embedded memory blocks, and DSP blocks.

Floorplan: The layout of physical resources on the device. Creating a design floorplan, or floorplanning, is the process of mapping logical design hierarchy to physical regions in the device.

Periphery logic: Logic resources on the device which include offchip I/O connections, such as transceivers, external memory interfaces, GPIOs, I/O receivers, and the HPS.

PR control block: A dedicated FPGA block. The PR control block processes the PR requests, handshake protocols, and verifies the cyclic redundancy check (CRC).

PR host: The system for coordinating PR. The PR host communicates with the PR control block. Implement the PR host within the FPGA (internal PR host) or in a chip or microprocessor (external PR host).

PR IP Core: The Intel® partial reconfiguration IP core that you instantiate in the static region of your design. This IP core interfaces with the PR control block to manage the bitstream source.

PR partition or reconfigurable design partition: A logical division in the source code hierarchy that you designate for PR. A PR project can contain one or more partially reconfigurable PR partitions.

PR persona: A specific configuration of a PR partition in a PR region. A PR region can support multiple personas. Static regions support only one persona.

PR region or LogicLock Plus region: A physical portion of the device that you choose to reconfigure. You can configure a device with more than one PR region. A PR region can only include core components such as LAB, RAM, or DSP. You associate a PR region with a PR partition in your design.

Revision: A collection of settings and constraints for one version of your project. A Quartus Prime Settings File (.qsf) preserves each revision of your project. Your Quartus Prime project can contain several revisions. A PR project includes a base revision, defining region boundaries and base logic, and one or more revisions defining different PR region implementations.

Snapshot: The output of a Compiler stage. The Quartus Prime Pro Edition Compiler generates a snapshot of the compiled database after each stage. The snapshot preserves the compilation database.

Static region: All areas outside the PR regions in your project. You associate the static region with the top-level partition of the design. The static region can contain both core and periphery locations in the device.

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