AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Creating the Device Tree Overlays

Three device tree overlay files are needed for this example. The first overlay updates the system description to add the new node containing the reconfigurable region. The other two overlays are used to describe the two PR region personas.

  1. Create a new file named base_static.dtso with the following contents. Note that the freeze Ccontroller type and base address must be entered into the appropriate fields. 
    
/dts-v1//plugin/;

/ {

  fragment@0 {
    target-path = "/soc/base_fpga_region";
    #address-cells = <0x1>;
    #size-cells = <0x1>;
    
    __overlay__ {
      ranges = <0x0 0x0 0xc0000000 0x40000 0x1 0x0 0xff200000 0x1000>;
      external-fpga-config;
      #address-cells = <0x2>;
      #size-cells = <0x1>;
      
      fpga_pr_region0 {
        compatible = "fpga-region";
        fpga-bridges = <&freeze_controller_0>;
        ranges;
      };
      
      freeze_controller_0: freeze_controller@0x100000450 {
        compatible = "altr,freeze_controller-16.1", \
          "altr,freeze-bridge-controller";
        reg = <0x1 0x450 0x10>;
      };
    };
  };
};
  2. Create a file named pr_region_default.dtso with the following contents. Note that the system ID peripheral base address is required. 
    
/dts-v1//plugin/;

/ {

  fragment@1 {
    target-path = "/soc/base_fpga_region/fpga_pr_region0";
    #address-cells = <0x1>;
    #size-cells = <0x1>;

    __overlay__ {
      partial-fpga-config;
      firmware-name = "pr_region_default.rbf";
      #address-cells = <0x2>;
      #size-cells = <0x1>;
      region-unfreeze-timeout-us = <0x4>;
      region-freeze-timeout-us = <0x4>;

      sysid@0x100000800 {
        compatible = "altr,sysid-16.1", "altr,sysid-1.0";
        reg = <0x1 0x800 0x8>;
      };
    };
  };
};
  3. Create a file named pr_region_alt.dtso with the following contents. Note that the system ID peripheral base address is different from the default persona. 
    
/dts-v1//plugin/;

/ {

  fragment@1 {
    target-path = "/soc/base_fpga_region/fpga_pr_region0";
    #address-cells = <0x1>;
    #size-cells = <0x1>;

    __overlay__ {
      partial-fpga-config;
      firmware-name = "pr_region_alt.rbf";
      #address-cells = <0x2>;
      #size-cells = <0x1>;
      region-unfreeze-timeout-us = <0x4>;
      region-freeze-timeout-us = <0x4>;

      sysid@0x100000A00 {
        compatible = "altr,sysid-16.1", "altr,sysid-1.0";
        reg = <0x1 0xA00 0x8>;
      };
    };
  };
};
  4. Load the embedded_command_shell.sh environment provided by the SoC EDS tools. This environment provides the device tree compiler command dtc. Use dtc to compile the newly created Device Tree Source (DTS) files to Device Tree Blob (DTB) files as shown below. 
    
$ dtc -@ -I dts -O dtb -o base_static.dtbo base_static.dtso
$ dtc -@ -I dts -O dtb -o pr_region_default.dtbo pr_region_default.dtso
$ dtc -@ -I dts -O dtb -o pr_region_alt.dtbo pr_region_alt.dtso
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