AN 798: Partial Reconfiguration with the Arria 10 HPS

Download PDF
ID 683034
Date 1/25/2017
Public

Visible to Intel only — GUID: gly1482303505490

Ixiasoft

View Details

Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Building the Base Revision with the Reconfigurable Design Partition

  1. Run the first two stages of the compilation flow (IP Generation and Analysis & Synthesis). This generates the design hierarchy so that the reconfigurable design partition and LogicLock Plus assignments can be added.
  2. To create a reconfigurable design partition, right-click the design instance of the PR region, point to Design Partition, and click Set as Reconfigurable Design Partition as shown below.
    Figure 24. Creating a Reconfigurable Design Partition
  3. To create a new LogicLock Plus region, similarly right-click the design instance, point to LogicLock Plus Region, and click Create New LogicLock Plus Region.
  4. Set the properties of the design partition and LogicLock Plus region using the editor windows.1 Edit the assignments as shown below. Change the design partition name to something generic, like “pr_region”. Make sure to adjust the LogicLock Plus placement, enable the Reserved and Core-Only attributes, and change the Routing Region type to Fixed with expansion of 1.
    For detailed information about design partition settings, refer to "Create Design Partitions for Partial Reconfiguration" in the Creating a Partial Reconfiguration Design chapter of the Quartus Prime Pro Edition Handbook Volume 1: Design and Compilation.
    Figure 25. Configure Partition and Region Properties
  5. Run a full compilation flow as follows:
    1. If the Compilation Dashboard is not visible, click Compilation Dashboard in the Tasks window.
    2. Click Compile Design.

    The following critical files are in the output_files/ directory after the compilation flow finishes:

    • pr_base.sof
    • pr_base.pr_region.pmsf

    These files contain the FPGA configuration images for the default complete FPGA and the PR region default persona, respectively. These files are converted to RBF images in a later step.

Related Information
1 If the editor windows are not visible, use the Assignments drop down menu to enable them.
Level Two Title