AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Hardware Tools and Methods

The PR design flow requires you to use the project revisions feature in the Quartus Prime Pro software. Your initial design is the base revision. In this revision, you define the physical boundaries in the device of the static region, which does not change under partial reconfiguration, and the reconfigurable regions, which do change.

From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions.

Figure 1. Regions and Personas

The implementation of an FPGA design with PR results in multiple FPGA configuration image files. One file is loaded initially, and the others are subsequently loaded to reconfigure FPGA logic. The first image loaded is an FPGA configuration containing the base static region and the default implementation, or persona, for each reconfigurable region. One additional configuration image is generated for each persona of each reconfiguration region. Loading one of these additional files causes the reconfiguration of the associated region to the alternate persona.

The management of reconfigurable logic regions is performed most efficiently using the FPGA Manager peripheral module within the HPS block, independent of the type of host software.

PR requires logical isolation of reconfigurable FPGA regions while they are being modified. This is called freeze logic.


Section Content
Arria 10 SoC Partial Reconfiguration Support
Overview of the Arria 10 GHRD

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