AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Implementing the Alternate Persona

In the following steps, you export the implemented base region and synthesized alternate persona regions as snapshots, and merge them into a complete PR design revision.

The snapshots are merged in the alternate persona implementation revision. The static snapshot is the scaffolding: the placed and routed static region, with an unused area set aside for the PR region. The persona is fitted and routed into that region. The persona snapshot is an unplaced and unrouted design, which is subsequently placed and routed into the PR region.

  1. In the main Quartus window, point to Project, and click Revisions from the drop down menu. Create a new revision for the PR alternate persona implementation configuration. Double click on << new revision >> and enter the revision information as shown below. Note this revision is based on the existing pr_base revision.
    Figure 29. Creating an Alternate Persona Revision
  2. Click OK to create the revision and open it as the current revision.
  3. To change the revision type of the new revision, point to Assignments, click Settings, choose the General category, and change the Revision Type field to Partial Reconfiguration – Persona Implementation as shown below.
    Figure 30. Setting the Alternate Persona Revision Type

    Because this is a Partial Reconfiguration – Persona Implementation type revision, the Quartus Pro tools do not allow the compilation stages before the fitter to run. Furthermore, some of the required compilation steps for this type of revision are not available in the Quartus Pro GUI window. You must compile this revision type from the command line.

  4. To compile the persona implementation, type the following commands: 
    
$ quartus_cdb ghrd_10as066n2 -c pr_base --export_pr_static_block \
root_partition --snapshot final --file pr_base_static.qdb
    The step above exports a snapshot (pr_base_static.qdb) of the PR static region design from the base revision. This design has been compiled, placed, and routed, and is used as a scaffolding to build the alternate personas. 
    
$ quartus_cdb ghrd_10as066n2 -c pr_alternate_synth --export_block \
root_partition --snapshot synthesized --file pr_alternate_synth.qdb
    The step above exports a snapshot (pr_alternate_synth.qdb) of the synthesized logic for the PR region alternate persona. This design is placed and routed using the scaffolding generated above. 
    
$ quartus_cdb ghrd_10as066n2 -c pr_alternate_fit --import_block \
root_partition --file pr_base_static.qdb
$ quartus_cdb ghrd_10as066n2 -c pr_alternate_fit --import_block \
pr_region --file pr_alternate_synth.qdb
    The steps above import the snapshots of the static place and route design, plus the synthesized alternate personal logic, into the current revision. 
    
$ quartus_fit ghrd_10as066n2 -c pr_alternate_fit
$ quartus_sta ghrd_10as066n2 -c pr_alternate_fit
$ quartus_asm ghrd_10as066n2 -c pr_alternate_fit
    The last steps complete the normal compilation flow starting with the fitter.
    After successful completion of the assembler stage, new files with the prefix pr_alternate_fit can be found in the output_files/ directory. These files contain reports and FPGA configuration images for the alternate persona.
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