Agilex™ 5 FPGA E-Series 065B Modular Development Kit User Guide

ID 820977
Date 7/12/2024
Public
Document Table of Contents

4.3.4.4.1. The COMP0 Tab

The COMP0 Test Tab

Figure 29. The COMP0 Test Tab

The following sections describe controls on this tab.

  • Start: Initiates DDR4 memory transaction test.
  • Stop: Terminates transaction test.
  • Test Control
    • Test Mode: Infinite Read and Write (default), Single Read and Write.
    • Success: Number of successful tests.
    • Fail: Number of failed tests.

The COMP0 Control Tab

Figure 30. The COMP0 Control Tab—Traffic Generator
  • Test Size: You can choose the size of the memory to test. The available options are 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB, 1 GB, 4 GB, and 8 GB (default).
  • Offset (Hex): You can define the memory start address to test.
  • Test Pattern: Preset for data pattern, like PRBS.
  • Test Program: Program for BTS (default), User Defined Program.
  • Program Name: Name of User Defined Program.
  • Generate Action: After setting above parameters, click this button to generate new instruction.
  • Update Action: Update new instruction to RAM.